Patent application number | Description | Published |
20090057810 | Method of Fabricating an Integrated Circuit - A method of fabricating an integrated circuit includes providing a semiconductor substrate having a doped area; generating a conductive structure towards the doped area, wherein the conductive structure includes an extending section that protrudes from the doped area; generating an electrically isolating layer at a sidewall of the extending section after generating the conductive structure. | 03-05-2009 |
20090236682 | LAYER STACK INCLUDING A TUNGSTEN LAYER - A method for producing a layer stack includes providing a tungsten layer, depositing an oxidation barrier layer that immunizes the tungsten layer against oxidation on top of the tungsten layer, and depositing a cap layer on top of the oxidation barrier layer. An integrated circuit is also described. | 09-24-2009 |
20100090285 | Integrated Circuit with a Contact Structure Including a Portion Arranged in a Cavity of a Semiconductor Structure - An integrated circuit includes a contact structure with a buried first and a protruding second portion. The buried first portion is arranged in a cavity formed in a semiconductor structure and is in direct contact with the semiconductor structure. The protruding second portion is arranged above the main surface of the semiconductor structure and in direct contact with a conductive structure that is spaced apart from or separated from the main surface of the semiconductor structure. An insulator structure is arranged below and in direct contact with the contact structure. | 04-15-2010 |
20120220086 | METHODS FOR FABRICATING A CMOS INTEGRATED CIRCUIT HAVING A DUAL STRESS LAYER (DSL) - Methods are provided for fabricating a CMOS integrated circuit having a dual stress layer without NiSi hole formation. One method includes depositing a tensile stress layer overlying a semiconductor substrate. A portion of the tensile stress layer is removed, leaving a remaining portion, before applying a curing radiation. A curing radiation is then applied to the remaining portion; and a compressive stress layer is deposited overlying the semiconductor substrate and the remaining portion. | 08-30-2012 |
20120261725 | Stabilized Metal Silicides in Silicon-Germanium Regions of Transistor Elements - Generally, the present disclosure is directed to methods of stabilizing metal silicide contact regions formed in a silicon-germanium active area of a semiconductor device, and devices comprising stabilized metal silicides. One illustrative method disclosed herein includes performing an activation anneal to activate dopants implanted in an active area of a semiconductor device, wherein the active area comprises germanium. Additionally, the method includes, among other things, performing an ion implantation process to implant ions into the active area after performing the activation anneal, forming a metal silicide contact region in the active area, and forming a conductive contact element to the metal silicide contact region. | 10-18-2012 |
20130052819 | Methods of Forming Metal Silicide Regions on Semiconductor Devices Using Different Temperatures - Disclosed herein are various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes. In one example, the method includes forming a plurality of N-doped source/drain regions and a plurality of P-doped source/drain regions in a semiconducting substrate and performing a first heating process at a first temperature to initially form a first metal silicide region in each of the P-doped source/drain regions. The method further includes performing a second heating process at a second temperature to initially form a second metal silicide region in each of the N-doped source/drain regions, wherein the second temperature is less than the first temperature and performing a third heating process at a third temperature to complete the formation of the first and second metal silicide regions, wherein the third temperature is greater than the first temperature. | 02-28-2013 |
20130058559 | METHOD AND APPARATUS FOR CHARACTERIZING DISCONTINUITIES IN SEMICONDUCTOR DEVICES - An approach is provided for characterizing discontinuities in semiconductor devices, for example in a metal silicide. An image of an integrated circuit is caused, at least in part, to be received. The image is analyzed for at least one discontinuity in the integrated circuit structure. A relative measure of the at least one discontinuity is determined in comparison to the integrated circuit structure based on analyzing the image. | 03-07-2013 |
20130122671 | PROCESS TO REMOVE Ni AND Pt RESIDUES FOR NiPtSi APPLICATIONS - The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Embodiments of the invention provide a multi-step cleaning process, comprising exposing the substrate to a nitric acid solution after a first anneal, followed by an aqua regia solution after a second anneal. The substrate can be optionally exposed to a hydrochloric acid solution afterward to completely remove any remaining platinum residues. | 05-16-2013 |
20130157450 | Methods of Forming Metal Silicide Regions on Semiconductor Devices - Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer. | 06-20-2013 |
20130234213 | NISI REWORK PROCEDURE TO REMOVE PLATINUM RESIDUALS - The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer, annealing the Ni removed Ni/Pt layer, removing unreacted Pt from the annealed Ni removed Ni/Pt layer, analyzing the Pt removed Ni/Pt layer for unreacted Pt residue, and if unreacted Pt residue is detected, applying SPM to the Pt removed Ni/Pt layer in a SWC tool. The SPM may be applied to the Pt removed Ni'/Pt layer at a temperature of 130° C. | 09-12-2013 |
20130234335 | HNO3 SINGLE WAFER CLEAN PROCESS TO STRIP NICKEL AND FOR MOL POST ETCH - Ni and Pt residuals are eliminated by replacing an SPM cleaning process with application of HNO | 09-12-2013 |
20130323890 | Aqua Regia and Hydrogen Peroxide HCl Combination to Remove Ni and NiPt Residues - A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate. | 12-05-2013 |
20140248770 | MICROWAVE-ASSISTED HEATING OF STRONG ACID SOLUTION TO REMOVE NICKEL PLATINUM/PLATINUM RESIDUES - A method is provided for removing residual Ni/Pt and/or Pt from a semiconductor substrate in a post salicidation cleaning process using microwave heating of a stripping solution. Embodiments include depositing a Ni/Pt layer on a semiconductor substrate; annealing the deposited Ni/Pt layer, forming a nickel/platinum silicide and residual Ni/Pt and/or Pt; removing the residual Ni/Pt and/or Pt from the semiconductor substrate by: microwave heating a strong acid solution in a non-reactive container; exposing the residual Ni/Pt and/or Pt to the microwave heated strong acid solution; and rinsing the semiconductor substrate with water H | 09-04-2014 |
20140363944 | Aqua Regia and Hydrogen Peroxide HCl Combination to Remove Ni and NiPt Residues - A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate. | 12-11-2014 |
20150017456 | Reducing voids caused by trapped acid on a dielectric surface - When an etchant for metal (e.g., HF) reaches an underlying silicon oxide layer, it may form silanol bonds or other hydrogen bonds that resist rinsing, so that some etchant remains to be trapped under the next deposited layer. Trapped etchant can create voids that eventually degrade the performance of the oxide layer. Exposing the surface to a liquid solution or gaseous precursor containing silane seals the defects without causing an overall thickness change. The silane reacts at sites with silanol (or other hydrogen) bonds, breaking the bonds and replacing the hydrogen with silicon, but does not react in the absence of a hydrogen bond. | 01-15-2015 |
20150044861 | GATE SILICIDATION - A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed. | 02-12-2015 |