Patent application number | Description | Published |
20080222339 | Processor architecture with switch matrices for transferring data along buses - There is described a processor architecture, comprising: a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction (for example, left to right) and a respective second bus running in a second direction opposite to the first direction (for example right to left); a plurality of second bus pairs, each second bus pair including a respective third bus running in a third direction (for example downwards) and a respective fourth bus running in a fourth direction opposite to the third direction (for example upwards), the third and fourth buses intersecting the first and second buses; a plurality of switch matrices, each switch matrix located at an intersection of a first and a second pair of buses; a plurality of elements arranged in an array, each element being arranged to receive data from a respective first or second bus, and transfer data to a respective first or second bus. The elements in the array include processing elements, for operating on received data, and memory elements, for storing received data. The described architecture has the advantage that it requires relatively little memory, and the memory requirements can be met by local memory elements in the array. | 09-11-2008 |
20120191945 | Processor Architecture With Switch Matrices For Transferring Data Along Buses - There is described a processor architecture, comprising: a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction (for example, left to right) and a respective second bus running in a second direction opposite to the first direction (for example right to left); a plurality of second bus pairs, each second bus pair including a respective third bus running in a third direction (for example downwards) and a respective fourth bus running in a fourth direction opposite to the third direction (for example upwards), the third and fourth buses intersecting the first and second buses; a plurality of switch matrices, each switch matrix located at an intersection of a first and a second pair of buses; a plurality of elements arranged in an array, each element being arranged to receive data from a respective first or second bus, and transfer data to a respective first or second bus. The elements in the array include processing elements, for operating on received data, and memory elements, for storing received data. The described architecture has the advantage that it requires relatively little memory, and the memory requirements can be met by local memory elements in the array. | 07-26-2012 |
Patent application number | Description | Published |
20080222339 | Processor architecture with switch matrices for transferring data along buses - There is described a processor architecture, comprising: a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction (for example, left to right) and a respective second bus running in a second direction opposite to the first direction (for example right to left); a plurality of second bus pairs, each second bus pair including a respective third bus running in a third direction (for example downwards) and a respective fourth bus running in a fourth direction opposite to the third direction (for example upwards), the third and fourth buses intersecting the first and second buses; a plurality of switch matrices, each switch matrix located at an intersection of a first and a second pair of buses; a plurality of elements arranged in an array, each element being arranged to receive data from a respective first or second bus, and transfer data to a respective first or second bus. The elements in the array include processing elements, for operating on received data, and memory elements, for storing received data. The described architecture has the advantage that it requires relatively little memory, and the memory requirements can be met by local memory elements in the array. | 09-11-2008 |
20120191945 | Processor Architecture With Switch Matrices For Transferring Data Along Buses - There is described a processor architecture, comprising: a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction (for example, left to right) and a respective second bus running in a second direction opposite to the first direction (for example right to left); a plurality of second bus pairs, each second bus pair including a respective third bus running in a third direction (for example downwards) and a respective fourth bus running in a fourth direction opposite to the third direction (for example upwards), the third and fourth buses intersecting the first and second buses; a plurality of switch matrices, each switch matrix located at an intersection of a first and a second pair of buses; a plurality of elements arranged in an array, each element being arranged to receive data from a respective first or second bus, and transfer data to a respective first or second bus. The elements in the array include processing elements, for operating on received data, and memory elements, for storing received data. The described architecture has the advantage that it requires relatively little memory, and the memory requirements can be met by local memory elements in the array. | 07-26-2012 |
Patent application number | Description | Published |
20130138791 | SESSION TRANSFER AND SUSPENSION IN A REMOTE ACCESS APPLICATION FRAMEWORK - Systems and method for providing for suspension and transfer of remote access sessions. In accordance with the methods, a request to suspend a session may be received at a server tier. The server tier prepares a URL that may be used at a later time by a client to resume the session. The URL is communicated to a client tier from which the request was received and, thereafter, a connection between the client tier and the server tier is closed. At a subsequent time, a request may be received to resume the session at the URL. After receipt of the request to resume the session, a connection with the requesting client tier is established by the server tier, and the session is resumed. | 05-30-2013 |
20140074913 | CLIENT-SIDE IMAGE RENDERING IN A CLIENT-SERVER IMAGE VIEWING ARCHITECTURE - Systems and methods within a remote access environment that enable a client device that is remotely accessing, e.g., medical images, to seamlessly switch from client-side rendering of image data to server-side rendering of the image data and vice-versa. Distributed image processing may be provided whereby image data may be streamed to, and processed by the client device (client-side rendering), or may be processed remotely at the server and downloaded to the client device for display (server-side rendering). The switching between the two modes may be based on predetermined criteria, such as network bandwidth, processing power the client device, type of imagery to be displayed. The environment also provides for collaboration among plural client devices where at least one of the plural client devices is performing client-side rendering. | 03-13-2014 |
20140184648 | DYNAMIC GENERATION OF TEST IMAGES FOR AMBIENT LIGHT TESTING - In a remote access environment that includes a server, a client device may remotely access, e.g., medical images from the server and may be provided with a mechanism to retrieve a test image, such as the TG-18 CT or TG-18 MP sample test patterns. The client device communicates display size information to the server, which generates the test image on-the-fly for the particular display size of the client device. For example, components in the test image and borders may be scaled to create an appropriate test image for any client device. | 07-03-2014 |
Patent application number | Description | Published |
20130240437 | NANOCOMPOSITE POLYMER-CARBON BASED NANOMATERIAL FILTERS FOR THE SIMULTANEOUS REMOVAL OF BACTERIA AND HEAVY METALS - The disclosed subject matter provides a filter that is modified by a polymer-carbon based nanomaterial nanocomposite intended to significantly enhance the performance of filtration, separation, and remediation of a broad variety of chemicals, heavy metal ions, organic matters, and living organisms. Polymeric materials, such as but not limited to poly-N-vinyl carbazole (PVK), are combined with (1) graphene (G) and/or graphene-like materials based nanomaterials and (2) graphene oxide (GO) chemically modified with a chelating agent such as but not limited to EDTA. The nanocomposite is homogenously deposited on the surface of the membrane. | 09-19-2013 |
20150182920 | NANOCOMPOSITE POLYMER-CARBON BASED NANOMATERIAL FILTERS FOR THE SIMULTANEOUS REMOVAL OF BACTERIA AND HEAVY METALS - The disclosed subject matter provides a filter that is modified by a polymer-carbon based nanomaterial nanocomposite intended to significantly enhance the performance of filtration, separation, and remediation of a broad variety of chemicals, heavy metal ions, organic matters, and living organisms. Polymeric materials, such as but not limited to poly-N-vinyl carbazole (PVK), are combined with (1) graphene (G) and/or graphene-like materials based nanomaterials and (2) graphene oxide (GO) chemically modified with a chelating agent such as but not limited to EDTA. The nanocomposite is homogenously deposited on the surface of the membrane. | 07-02-2015 |