| Patent application number | Description | Published |
|---|
| 20080220998 | REVERSIBLE THERMAL THICKENING GREASE - A reversible thermal thickening grease for microelectronic packages, in which the grease contains filler particles; at least one polymer; and a binder; in which the filler particles are dispersed within the binder, in which one or more segments of the at least one polymer may be attached to the filler particles prior to dispersion in the binder, and in which the polymer collapses at temperatures below a Theta temperature and swells at temperatures above a Theta temperature. During the operation of a microelectronic package, grease pump-out and air proliferation are minimized with use of the reversible thermal thickening grease, while grease fluidity is retained under repetitive thermal stresses. | 09-11-2008 |
| 20080231311 | PHYSICALLY HIGHLY SECURE MULTI-CHIP ASSEMBLY - A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts. | 09-25-2008 |
| 20080265445 | Marks for the Alignment of Wafer-Level Underfilled Silicon Chips and Method to Produce Same - A semiconductor wafer and the process for aligning wafer level underfill material coated chips with a substrate via alignment marks made visible through laser dicing. | 10-30-2008 |
| 20080284052 | VACUUM EXTRUSION METHOD OF MANUFACTURING A THERMAL PASTE - A method of manufacturing a thermal paste, in which the method includes feeding the thermal paste into a chamber of an extruder; mixing the thermal paste at elevated temperatures; de-airing the thermal paste; and extruding the thermal paste out of the chamber through a die as a pre-form or into a cartridge, such that air channels and pseudo-grain boundaries are prevented from forming in the thermal paste. | 11-20-2008 |
| 20090032962 | CENTRIFUGAL METHOD FOR FILING HIGH ASPECT RATIO BLIND MICRO VIAS WITH POWDERED MATERIALS FOR CIRCUIT FORMATION - The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component. | 02-05-2009 |
| 20090080833 | APPARATUS AND METHODS FOR REMAKEABLE CONNECTIONS TO OPTICAL WAVEGUIDES - A single-mode optical waveguide with a core, surrounded by a cladding consisting of an inner soft layer and an outer harder layer is described. The outer layer has a grating structure on its inner surface, whose spatial frequency is the same as that of the guided mode. The thickness of the inner cladding is sufficient to keep the grating outside the mode field in undeformed regions of the waveguide, so that normally no out-coupling of the light results. Connections are made by crossing two such waveguides at an angle and pressing them together. This results in deformation of the two waveguides such that the gratings are brought into proximity with the cores. Light is coupled out of one waveguide and into the other in the deformed region, resulting in a self-aligning optical connection. The out-coupled light propagates normal to the waveguide axis, so errors in the crossing angle cause little change in efficiency. Because the cladding system is sufficiently resilient to recover after deformation, the connection is remakeable. | 03-26-2009 |
| 20090102070 | Alignment Marks on the Edge of Wafers and Methods for Same - A semiconductor wafer having alignment marks a sufficient distance from the outer wafer edge that reference dicing channels and a method for same. A process for dicing WLUF coated wafers into singulated chips using said alignment marks on the outer edge of the wafer. | 04-23-2009 |
| 20090108472 | WAFER-LEVEL UNDERFILL PROCESS USING OVER-BUMP-APPLIED RESIN - A process of fabricating wafer-level underfilled microelectronic packages using over-bump application of a self-fluxing resin to a wafer, b-staging of the resin, dicing of the coated wafer, and joining the diced chips to substrates producing wafer-level underfilled microelectronic flip-chip packages. Moreover, provided are microelectronic packages, which are produced in accordance with the inventive process. | 04-30-2009 |
| 20090251698 | METHOD AND SYSTEM FOR COLLECTING ALIGNMENT DATA FROM COATED CHIPS OR WAFERS - A process and system for determining alignment data for features on wafers or chips when a wafer or chip is substantially coated by an over bump applied material, e.g. a resin or film, and using that data to align the wafers or chips for subsequent operations such as dicing or joining. Position data for alignment is produced by identifying a location of an at least partially obscured feature by varying the depth of focus upon a work piece to determine an SNR approximating a maximum value from an image captured by optical scanning. An SNR above a threshold value can be employed. | 10-08-2009 |
| 20100003786 | CHIP-LEVEL UNDERFILL PROCESS AND STRUCTURES THEREOF - A process comprises forming a first electrical interconnect structure on a surface of a singulated semiconductor chip having an alignment pattern. The alignment pattern is scanned and stored in a scanning device prior to application of a curable underfill coating to the surface of the singulated semiconductor chip. This is followed by applying a curable underfill coating to the surface of the singulated semiconductor chip to produce a coated semiconductor chip. The process also includes a step of delivering the scanned and stored alignment pattern to an alignment and joining device positioned adjacent to and operatively associated with a substrate having a second electrical interconnect structure alignable to make electrical contact with the first electrical interconnect structure. The coated semiconductor chip is placed in the alignment and joining device so that when the scanned and stored alignment pattern is activated the alignment and joining device positions the coated semiconductor chip so that the first electrical interconnect structure is aligned to make electrical contact with the second electrical interconnect structure. This is followed by activating the alignment and joining device to join the coated semiconductor chip to the substrate so that the first electrical interconnect structure is in electrical contact with the second electrical interconnect structure. In one embodiment, the first electrical interconnect structure is placed on a surface of a semiconductor chip array in a wafer to produce the electrically connectable semiconductor structure which is followed by dicing to produce at least one of the singulated semiconductor chips. Another embodiment comprises aligning the fist and second electrical interconnect structures prior to applying the curable underfill coating. | 01-07-2010 |
| 20100164030 | CHIP CARRIER BEARING LARGE SILICON FOR HIGH PERFORMANCE COMPUTING AND RELATED METHOD - Embodiments of the present invention provide a system and method for manufacturing integrated circuit (IC) chip packages. In one embodiment, the integrated circuit (IC) chip package can include an IC chip and a substrate coupled to the IC chip. The substrate can include a glass fiber re-enforced epoxy core, a plurality copper circuitry containing particle re-enforced epoxy layers symmetrically-oriented to each surface of the glass fiber re-enforced epoxy core, and an outermost amorphous glass layer on each surface of the plurality of layers. The IC chip can be coupled to copper circuitry bonded to one of the outermost amorphous glass layers. | 07-01-2010 |
