Patent application number | Description | Published |
20110148876 | Compiling for Programmable Culling Unit - During compilation, the interval bounds for a programmable culling unit are calculated if possible. For each variable, interval bounds are calculated during the compilation, and the bounds together with other metadata are used to generate an optimized culling program. If not possible, then an assumption may be made and the assumption used to compile the code. If the assumption proves to be invalid, a new assumption could be made and the code may be recompiled in some embodiments. | 06-23-2011 |
20120075303 | Multi-View Ray Tracing Using Edge Detection and Shader Reuse - A multi-view image may be generated by detecting discontinuities in a radiance function using multi-view silhouette edges. A multi-view silhouette edge is an edge of a triangle that intersects a back tracing plane and, in addition, the triangle faces backwards, as seen from the intersection point, and the edge is not further connected to any back facing triangles. Analytical visibility may be computed between shading points and a camera line and shared shading computations may be reused. | 03-29-2012 |
20120201467 | Stream Compaction for Rasterization - A single instruction multiple data (SIMD) processor with a given width may operate on registers of the same width completely filled with fragments. A parallel set of registers are loaded and tested. The fragments that fail are eliminated and the register set is refilled from the parallel set. | 08-09-2012 |
20120218264 | Hierarchical Motion Blur Rasterization - Motion blur rasterization may involve executing a first test for each plane of a tile frustum. The first test is a frustum plane versus moving bounding box overlap test where planes bounding a moving primitive are overlap tested against a screen tile frustum. According to a second test executed after the first test, for primitive edges against tile corners, the second test is a tile corner versus moving edge overlap test. The corners of the screen space tile are tested against a moving triangle edge in two-dimensional homogeneous space. | 08-30-2012 |
20120293515 | Rendering Tessellated Geometry With Motion and Defocus Blur - A moving or defocused geometry may be stochastically rendered by grouping a plurality of primitives of that geometry in a hierarchical data structure. Visible fragments may be located in that data structure by hierarchically traversing a ray frustum through the structure. A time-dependent ray tracing data structure may be used in some embodiments. | 11-22-2012 |
20130265301 | Sample Culling Based on Linearized 5D Edge Equations - Thin invention introduces a five-dimensional rasterization technique that uses a test based on triangle edges in order to obtain high efficiency. A compact formulation of five-dimensional edge equations is used to derive a conservative triangle edge versus tile test in five dimensions, expressed as an affine hyperplane. | 10-10-2013 |
20130271465 | Sort-Based Tiled Deferred Shading Architecture for Decoupled Sampling - A graphics pipeline combines the benefits of decoupling sampling with deferred shading. In the rasterization phase, a shading point is computed for each sample. After rasterization is finished, the shading points are sorted to extract coherence and groups of shading points shaded. This enables high sampling rates with efficient reuse of shading, in addition to other unique benefits. | 10-17-2013 |
20140184597 | Generating Random Sampling Distributions Using Stochastic Rasterization - Stochastic rasterization may be used as a flexible volumetric sampling mechanism. By bounding and tessellating the sampling domain, uniform sampling distributions over an arbitrary domain can be efficiently generated in up to five dimensions. Sample placement allows pseudo-random, stratified random, or blue noise sampling. Random sampling with an adaptive density function may be achieved by adding one dimension. | 07-03-2014 |
20140300619 | Programmable Tile Shader - In accordance with some embodiments, a tile shader executes on a group of pixels prior to a pixel shader. The tile of pixels may be rectangular in some embodiments. The tile may be executed hierarchically, refining each tile into smaller subtiles until the pixel or sample level is reached. The tile shader program can be written to discard groups of pixels, thereby quickly removing areas of the bounding triangles that lie outside the shape being rasterized or quickly discarding groups of pixel shader executions that will not contribute to the final image. | 10-09-2014 |
20140320495 | Rendering Tessellated Geometry With Motion and Defocus Blur - A moving or defocused geometry may be stochastically rendered by grouping a plurality of primitives of that geometry in a hierarchical data structure. Visible fragments may be located in that data structure by hierarchically traversing a ray frustum through the structure. A time-dependent ray tracing data structure may be used in some embodiments. | 10-30-2014 |
20150022532 | Hierarchical Motion Blur Rasterization - Motion blur rasterization may involve executing a first test for each plane of a tile frustum. The first test is a frustum plane versus moving bounding box overlap test where planes bounding a moving primitive are overlap tested against a screen tile frustum. According to a second test executed after the first test, for primitive edges against tile corners, the second test is a tile corner versus moving edge overlap test. The corners of the screen space tile are tested against a moving triangle edge in two-dimensional homogeneous space. | 01-22-2015 |
20150070355 | Adaptive Multi-Frequency Shading - An architecture for pixel shading, enables flexible control of shading rates and automatic shading reuse between triangles in tessellated primitives in some embodiments. The cost of pixel shading may then be decoupled from the geometric complexity. Wider use of tessellation and fine geometry may be made more feasible, even at very limited power budgets. Shading may be done over small local grids in parametric patch space, with reusing of shading for nearby samples. The decomposition of shaders into multiple parts is supported, which parts are shaded at different frequencies. Shading rates can be locally and adaptively controlled, in order to direct the computations to visually important areas and to provide performance scaling with a graceful degradation of quality. Another important benefit, in some embodiments, of shading in patch space is that it allows efficient rendering of distribution effects, which further closes the gap between real-time and offline rendering. | 03-12-2015 |
20150084981 | Anti-Aliasing for Graphics Hardware - Visibility may be analytically resolved rather than using point-sampling, thereby entirely avoiding geometric aliasing and the need to store multiple samples per pixel. By relying on existing techniques for shading, i.e., by shading once per fragment and focusing on visibility, visual results may be equivalent to multi-sampled anti-aliasing (MSAA) using an infinite sampling rate in some embodiments. | 03-26-2015 |
Patent application number | Description | Published |
20090046935 | IMAGE PROCESSING - First and second codewords are determined, based on first feature vector components of the image elements in an image block, as representations of a first and second component value. Third and fourth codewords are determined, based on second vector components, as representations of a third and fourth component value. First N | 02-19-2009 |
20090160857 | Unified Compression/Decompression Graphics Architecture - A unified compression/decompression architecture is disclosed for reducing memory bandwidth requirements in 3D graphics processing applications. The techniques described erase several distinctions between a texture (compressed once, and decompressed many times), and buffers (compressed and decompressed repeatedly during rendering of an image). An exemplary method for processing graphics data according to one or more embodiments of the invention thus begins with the updating of one or more tiles of a first image array, which are then compressed, using a real-time buffer compression algorithm, to obtain compressed image array tiles. The compressed image array tiles are stored for subsequent use as a texture. During real-time rendering of a second image array, the compressed image array tiles are retrieved and decompressed using a decompression algorithm corresponding to the buffer compression algorithm. The decompressed image array tiles are then applied as a texture to one or more primitives in the second image array. | 06-25-2009 |
20100060629 | Graphics-Processing Architecture Based on Approximate Rendering - A graphics processing circuit for rendering three-dimensional graphics data is disclosed. The circuit includes pipelined graphics processing stages, wherein each of two or more of the stages is configured to process at least one of graphics primitives, vertices, tiles, and pixels, according to a stage-specific error budget. Depending on its error budget, each of these stages may select a high- or low-precision calculation, select between lossless and lossy compression, adjust the compression ratio of a variable lossy compression algorithm, or some combination of these approaches. The circuit further comprises a global error-control unit configured to determine error budgets for each of the two or more stages, based on at least one of error data received from the two or more stages, predetermined scene complexity data, and user-defined error settings, and to assign the error budgets to the graphics processing stages. Corresponding methods for processing graphics data are also disclosed. | 03-11-2010 |
20100097377 | Graphics Processing Using Culling on Groups of Vertices - A first representation of a group of vertices may be received and a second representation of said group of vertices may be determined based on said first representation. A first set of instructions may be executed on said second representation of the group of vertices for providing a third representation of said group of vertices. The first set of instructions is associated with vertex position determination. The third representation of the group of vertices is subjected to a culling process. | 04-22-2010 |
20110018874 | Method, Apparatus, and Computer Program Product For Improved Graphics Performance - A method for improving performance of generation of digitally represented graphics. The method comprises: receiving a first representation of a base primitive; providing a set of instructions associated with vertex position determination; executing said retrieved set of instructions on said first representation of said base primitive using bounded arithmetic for providing a second representation of said base primitive, and subjecting said second representation of said base primitive to a culling process. A corresponding apparatus and computer program product are also presented. | 01-27-2011 |
20130251276 | USING RESOLUTION NUMBERS TO DETERMINE ADDITIONAL COMPONENT VALUES - First and second codewords are determined, based on first feature vector components of the image elements in an image block, as representations of a first and second component value. Third and fourth codewords are determined, based on second vector components, as representations of a third and fourth component value. First N | 09-26-2013 |