Patent application number | Description | Published |
20080296725 | SEMICONDUCTOR COMPONENT AND METHOD FOR FABRICATING THE SAME - A semiconductor component includes a substrate, two isolation structures, a conductor pattern and a dielectric layer. The isolation structures are disposed in the substrate, and each of the isolation structures has protruding portions protruding from the surface of the substrate. A trench is formed between the protruding portions. The included angle formed by the sidewall of the protruding portion and the surface of the substrate is an obtuse angle. The conductor pattern is disposed in the trench and fills the trench up. The dielectric layer is disposed between the conductor pattern and the substrate. | 12-04-2008 |
20090146101 | ETCHANT FOR METAL ALLOY HAVING HAFNIUM AND MOLYBDENUM - An etchant for etching a metal alloy having hafnium and molybdenum includes 20 to 80 percent by weight of nitric acid, 1 to 49 percent by weight of hydrofluoric acid, 1 to 96 percent by weight of sulfuric acid, and 1 to 30 percent by weight of water, based on the total weight of the etchant. | 06-11-2009 |
20090166703 | MEMORY DEVICE WITH A LENGTH-CONTROLLABLE CHANNEL - A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending away from a top surface of the substrate, a first doping region formed on a side of the upper portion of the trench in the substrate for serving as source/drain, a conductive layer formed in the trench and electrically connected to the first doping region, a top dielectric layer formed on conductive layer, a gate formed on the top dielectric layer, an epitaxy layer formed on both sides of the gate and on the substrate and a second doping area formed on a top of the epitaxy layer for serving as source/drain. | 07-02-2009 |
20110101448 | VERTICAL TRANSISTOR AND MANUFACTURING METHOD THEREOF - A vertical transistor includes: a substrate, a bottom-oxide layer, an epitaxial silicon layer, an insulating oxide layer, two gate-oxide films and a gate-stacked layer. The bottom-oxide layer is disposed on the substrate, and the bottom-oxide layer has a gate recess concavely formed thereof. The substrate has a first doped area in an upper part corresponding to the gate recess. The epitaxial silicon layer is formed on the gate recess, and the epitaxial silicon layer has a second doped area in an upper part. The insulating oxide layer is disposed on the epitaxial silicon layer. The gate-oxide films are respectively formed on two opposite sides of the epitaxial silicon layer. The gate-stacked layer is formed on the two gate-oxide layers and the bottom-oxide layer. Whereby, the lateral area of transistor is reduced, and the integration and the performance of the device are improved. | 05-05-2011 |
20110133248 | VERTICAL PMOS FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The mesa structure includes a first strained Si—Ge layer, an epitaxial Si layer and a second strained Si—Ge layer. The first strained Si—Ge layer is located on the oxide layer and the first nitride layer. The epitaxial Si layer is located on the first strained Si—Ge layer. The second strained Si—Ge layer is located on the epitaxial Si layer. In the surface layer of the second strained Si—Ge layer, there is a second doping area. The two gate oxide films are located at two sides of the mesa structure. | 06-09-2011 |
20110156285 | INTEGRATED ALIGNMENT AND OVERLAY MARK, AND METHOD FOR DETECTING ERRORS OF EXPOSED POSITIONS THEREOF - An integrated alignment and overlay mark for detecting the exposed errors of the photolithography process between a pre-layer and a current layer is disclosed. The integrated alignment and overlay mark includes an alignment mark and an overlay mark in the same shot region. The alignment mark is formed surrounding the overlay mark; therefore, the gap or the orientation between the pre-layer and the current layer can be calculated in order to check the alignment accuracy of photolithography process. | 06-30-2011 |
20110226736 | METHOD OF PATTERNING METAL ALLOY MATERIAL LAYER HAVING HAFNIUM AND MOLYBDENUM - A method of patterning a metal alloy material layer having hafnium and molybdenum. The method includes forming a patterned mask layer on a metal alloy material layer having hafnium and molybdenum on a substrate. The patterned mask layer is used as a mask and an etching process is performed using an etchant on the metal alloy material layer having hafnium and molybdenum so as to form a metal alloy layer having hafnium and molybdenum. The etchant includes at least nitric acid, hydrofluoric acid and sulfuric acid. The patterned mask layer is removed. | 09-22-2011 |
20120313157 | DRAM CELL HAVING BURIED BIT LINE AND MANUFACTURING METHOD THEREOF - A dram cell having buried bit line includes a substrate having fin structures thereon, a plurality of deep trenches in the substrate, a buried stripe, a plurality of word lines formed on the substrate and a plurality of capacitors formed on the fin structures. Each of the deep trenches is arranged between two adjacent fin structures. Each of the deep trenches has a metal layer and a poly-silicon layer thereinside to define a buried bit line. The buried stripe is formed in the substrate and next to each of the deep trenches. The bit line is electrically connected to the corresponding fin structure via the buried stripe. The word lines are alternatively arranged with the bit lines, and each of the word lines are disposed cross on the fin structures to construct double gate structures. | 12-13-2012 |
20140117442 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes multiple buried gates which are disposed in a substrate and have a first source and a second source, an interlayer dielectric layer covering the multiple buried gates and the substrate as well as a core dual damascene plug including a first plug, a second plug and an insulating slot. The insulating slot is disposed between the first plug and the second plug so that the first plug and the second plug are mutually electrically insulated. The first plug and the second plug respectively penetrate the interlayer dielectric layer and are respectively electrically connected to the first source and the second source. | 05-01-2014 |
20140124844 | SEMICONDUCTOR LAYOUT STRUCTURE - A semiconductor layout structure includes multiple active blocks which are disposed on a substrate, parallel with one another and extending along a first direction, multiple first shallow trench isolations which are disposed on a substrate, parallel with one another and respectively disposed on the multiple active blocks, and multiple second shallow trench isolations which are disposed on a substrate, cutting through multiple active blocks and extending along a second direction. The first direction has an angle about 1 degree to about 53 degrees to the second direction. | 05-08-2014 |
20140252550 | STACK CAPACITOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides a stack capacitor structure and a manufacturing method thereof, adapted for a random access memory. The stack capacitor structure is formed on a semiconductor substrate. The stack capacitor structure includes an oxide layer and a circular-shaped stopping layer. The oxide layer is disposed on the semiconductor substrate. The oxide layer has a capacitor trench therein. The circular-shaped stopping layer surrounds an edge of an opening of the capacitor trench. The disclosed stack capacitor structure and the manufacturing method thereof may thereby prevent the occurrence of the stack capacitor structure from having CD variation and belly region causing cell to cell leakage as result of manufacturing process limitation. | 09-11-2014 |
20140291729 | MEMORY UNIT, MEMORY UNIT ARRAY AND METHOD OF MANUFACTURING THE SAME - A memory unit includes a substrate, at least one charge storage element, at least one first recessed access element, and an isolation portion. The substrate has a surface and the first recessed access element is disposed in an active area of the substrate and extending from the surface into the substrate. The first recessed access element is electrically connected to the charge storage element and induces in the substrate a first depletion region. The isolation portion is adjacent to the active area and extending from the surface into the substrate. The isolation portion includes a trenched isolating barrier and a second recessed access element. The second recessed access element is disposed in the trenched isolating barrier and induces in the substrate a second depletion region merging with the first depletion region. | 10-02-2014 |
20140291738 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor electronic device structure includes an active area array disposed in a substrate, an isolation structure, a plurality of recessed gate structures, a plurality of word lines, and a plurality of bit lines. The active area array a plurality of active area columns and a plurality of active area rows, defining an array of active areas. The substrate has two recesses formed at the central region thereof. Each recessed gate structure is respectively disposed in the recess. A protruding structure is formed on the substrate in each recess. A STI structure of the isolation structure is arranged between each pair of adjacent active area rows. Word lines are disposed in the substrate, each electrically connecting the gate structures there-under. Bit lines are disposed above the active areas, forming a crossing pattern with the word lines. | 10-02-2014 |