| Patent application number | Description | Published |
|---|
| 20080224228 | CAPACITOR TOP PLATE OVER SOURCE/DRAIN TO FORM A 1T MEMORY DEVICE - A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed over a portion of the active area. A source element and a drain element in the substrate adjacent to the gate electrode. The drain element is comprised of a drain region and a bottom plate region. The drain region is between the bottom plate region and the gate structure. A capacitor dielectric and a capacitor top plate are over at least portions of the bottom plate region. | 09-18-2008 |
| 20080315317 | SEMICONDUCTOR SYSTEM HAVING COMPLEMENTARY STRAINED CHANNELS - A semiconductor system is provided including providing a semiconductor substrate; forming PMOS and NMOS transistors in and on the semiconductor substrate; forming a tensile strained layer on the semiconductor substrate; and relaxing the tensile strained layer around the PMOS transistor. | 12-25-2008 |
| 20090026549 | METHOD TO REMOVE SPACER AFTER SALICIDATION TO ENHANCE CONTACT ETCH STOP LINER STRESS ON MOS - An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors. | 01-29-2009 |
| 20090050972 | Strained Semiconductor Device and Method of Making Same - A method of making a semiconductor device is disclosed. A semiconductor body, a gate electrode and source/drain regions are provided. A liner is provided that covers the gate electrode and the source/drain regions. Silicide regions are formed on the semiconductor device by etching a contact hole through the liner. | 02-26-2009 |
| 20090146181 | INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFUSED SOURCE/DRAIN EXTENSIONS - An integrated circuit system that includes: providing a PFET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer. | 06-11-2009 |
| 20090146262 | INTEGRATED CIRCUIT SYSTEM EMPLOYING SELECTIVE EPITAXIAL GROWTH TECHNOLOGY - An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to form a trench spacer; and depositing an epitaxial growth within the trench that includes a crystalline orientation that is substantially identical to the substrate. | 06-11-2009 |
| 20090206408 | NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE - A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, R | 08-20-2009 |
| 20090236663 | HYBRID ORIENTATION SUBSTRATE WITH STRESS LAYER - A hybrid orientation substrate includes a base substrate having a first orientation, a first surface layer having a first orientation disposed on the base substrate in a first region, and a second surface layer disposed on the base substrate in a second region. The second surface layer has an upper sub-layer having a second orientation, and a lower sub-layer between the base substrate and the upper sub-layer. The lower sub-layer having a first stress induces a second stress on the upper sub-layer. | 09-24-2009 |
| 20090261448 | METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURES FOR INTEGRATED CIRCUITS - A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is performed by non-selectively etching the substrate to deepen the preliminary openings to form STI gaps with substantially flat bottoms. | 10-22-2009 |
| 20090289379 | Methods of Manufacturing Semiconductor Devices and Structures Thereof - Methods of manufacturing semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming recesses in a first region and a second region of a workpiece. The first region of the workpiece is masked, and the recesses in the second region of the workpiece are filled with a first semiconductive material. The second region of the workpiece is masked, and the recesses in the first region of the workpiece are filled with a second semiconductive material. | 11-26-2009 |
| 20100009502 | Semiconductor Fabrication Process Including An SiGe Rework Method - A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C. | 01-14-2010 |
| 20100009527 | INTEGRATED CIRCUIT SYSTEM EMPLOYING SINGLE MASK LAYER TECHNIQUE FOR WELL FORMATION - A method for manufacturing an integrated circuit system that includes: providing a substrate; forming a mask layer over the substrate; implanting a first well through an opening in the mask layer into the substrate; and implanting a second well through the mask layer and the opening via a single implant into the substrate. | 01-14-2010 |
| 20100059831 | Spacer-less Low-K Dielectric Processes - A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator. | 03-11-2010 |
| 20100081259 | DISLOCATION ENGINEERING USING A SCANNED LASER - A method for generating patterned strained regions in a semiconductor device is provided. The method includes directing a light-emitting beam locally onto a surface portion of a semiconductor body; and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam, the light-emitting beam being characterized as having a scan speed, so as to produce the patterned strained regions. | 04-01-2010 |
| 20100187587 | MEMORY CELL STRUCTURE AND METHOD FOR FABRICATION THEREOF - A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate. | 07-29-2010 |
| 20100197093 | STRESS OPTIMIZATION IN DUAL EMBEDDED EPITAXIALLY GROWN SEMICONDUCTOR PROCESSING - A method of manufacturing dual embedded epitaxially grown semiconductor transistors is provided, the method including depositing a first elongated oxide spacer over first and second transistors of different types, depositing a first elongated nitride spacer on the first oxide spacer, depositing a first photoresist block on the nitride spacer above the first transistor, etching the first nitride spacer above the second transistor, implanting a first halo around the second transistor, etching a first recess in an outer portion of the first halo, stripping the first photoresist above the first transistor, forming a first epitaxially grown semiconductor material in the first recess, implanting a first extension in a top portion of the first material, depositing an elongated blocking oxide over the first and second transistors and first extension, depositing a second photoresist block on the blocking oxide above the second transistor and first extension, etching the blocking oxide and first nitride spacer above the first transistor, implanting a second halo around the first transistor, etching a second recess in an outer portion of the second halo, stripping the second photoresist above the second transistor, forming a second epitaxially grown semiconductor material in the second recess, implanting a second extension in a top portion of the second material, etching the blocking oxide above the second transistor, etching nitride caps from the first and second transistors, depositing a second elongated oxide spacer on the first and second transistors, depositing a second elongated nitride spacer on the second oxide spacer, etching the second nitride spacer to leave nitride sidewalls around gates of the first and second transistors, and implanting deep sources and drains in the first and second transistors. | 08-05-2010 |
| 20100301424 | NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE - A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, R | 12-02-2010 |
