| Patent application number | Description | Published |
|---|
| 20080305594 | METHOD FOR FABRICATING NON-VOLATILE MEMORY - A method for fabricating a non-volatile memory is provided. Parallel-arranged isolation structures are disposed in a substrate and protrude from the surface of the substrate to define active regions. Mask layers intersecting the isolation structures are deposited on the substrate. The surface of the mask layers is higher than that of the isolation structures. Doped regions are formed in the substrate. Insulating layers are deposited on the substrate between the mask layers. The insulating layers and the mask layers have different etch selectivities. The mask layers are removed to expose the substrate. A tunneling dielectric layer is formed on the substrate. A floating gate is deposited on the substrate surrounded by the isolation structures and the insulating layers. The surface of the floating gate is lower than that of the isolation structures. An inter-gate dielectric layer is deposited on the substrate. A control gate is disposed between the insulating layers. | 12-11-2008 |
| 20090053870 | METHOD FOR PREPARING FLASH MEMORY STRUCTURES - A method for preparing a flash memory structure comprises the steps of forming a plurality of dielectric blocks having block sidewalls on a substrate, forming a plurality of first spacers on the block sidewalls of the dielectric blocks, removing a portion of the substrate not covered by the dielectric blocks and the first spacers to form a plurality of trenches in the substrate, performing a deposition process to form an isolation dielectric layer filling the trenches, removing the dielectric blocks to expose spacer sidewalls of the first spacers, forming a plurality of second spacers on the spacer sidewalls of the first spacers, and removing a portion of the substrate not covered by the first spacers, the second spacers and the isolation dielectric layer to form a plurality of second trenches in the substrate. | 02-26-2009 |
| 20100062593 | METHOD FOR PREPARING MULTI-LEVEL FLASH MEMORY DEVICES - A method for preparing a multi-level flash memory device comprises forming a dielectric stack including a charge-trapping layer on a semiconductor substrate, forming an insulation structure having a depression on the charge-trapping layer, removing a portion of the charge-trapping layer from the depression such that the charge-trapping layer is segmented to form a plurality of storage nodes, forming a gate oxide layer isolating the storage nodes and forming a damascene gate including a polysilicon layer filling the depression. | 03-11-2010 |
| 20100106425 | SOLID-STATE UREA BIOSENSOR AND ITS DATA ACQUISITION SYSTEM - A data acquisition system for a solid-state urea biosensor uses an amplifier, a low-pass filter and a data acquisition card to acquire and relay data to a computer to be analyzed by a signal analysis program and displayed on a display panel. The biosensor includes a substrate, and three individual sensing areas separated by an insulating layer on the substrate. Each individual sensing area contains a conductive layer on the substrate, and a pH sensitive membrane is deposited thereon. An enzyme layer is deposited on one of the pH sensitive membranes to form a working electrode. The other two sensing areas are a quasi-reference electrode and a contrast electrode, respectively. The signals are transferred to an instrumentation amplifier. The amplified signals are then transferred to a low-pass filter. The filtered signals are analyzed by the program and then displayed on the display panel. | 04-29-2010 |
