| Patent application number | Description | Published |
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| 20100205408 | Speculative Region: Hardware Support for Selective Transactional Memory Access Annotation Using Instruction Prefix - A computer system and method is disclosed for executing selectively annotated transactional regions. The system is configured to determine whether an instruction within a plurality of instructions in a transactional region includes a given prefix. The prefix indicates that one or more memory operations performed by the processor to complete the instruction are to be executed as part of an atomic transaction. The atomic transaction can include one or more other memory operations performed by the processor to complete one or more others of the plurality of instructions in the transactional region. | 08-12-2010 |
| 20110040906 | Multi-level Buffering of Transactional Data - An apparatus, method, and system for implementing a hardware transactional memory (HTM) system with multiple levels of transactional buffers. The apparatus comprises a data cache configured to buffer data in a shared (by a plurality of processing cores) memory accessed by speculative memory access operations and to retain the data during at least a portion of an attempt to execute the atomic memory transaction. The apparatus also comprises an overflow detection circuit configured to detect an overflow condition upon determining that the data cache has insufficient capacity to buffer a portion of data accessed as part of the atomic memory transaction, as well as a buffering circuit configured to respond to the detection of the overflow condition by preventing the portion of data from being buffered in the data cache and buffering the portion of data in a secondary buffer separate from the data cache. | 02-17-2011 |
| 20110040913 | USER-LEVEL INTERRUPT MECHANISM FOR MULTI-CORE ARCHITECTURES - A method includes accepting for a first processor core of a plurality of processor cores in a multi-core system, a user-level interrupt indicated by a user-level interrupt message when an interrupt domain of an application thread executing on the first processor core and a recipient identifier of the application thread executing on the first processor core match corresponding fields in the user-level interrupt message. | 02-17-2011 |
| 20110040914 | MECHANISM FOR RECORDING UNDELIVERABLE USER-LEVEL INTERRUPTS - A method includes recording a user-level interrupt as undeliverable in a mailbox at least partially based on an interrupt domain identifier and an interrupt recipient identifier included in a user-level interrupt message associated with the user-level interrupt. The recording is at least partially based on an indication that the user-level interrupt is undeliverable to a recipient application thread executing on a processor core of a plurality of processor cores in a multi-core system. | 02-17-2011 |
| 20110040915 | FLEXIBLE NOTIFICATION MECHANISM FOR USER-LEVEL INTERRUPTS - A method includes delivering a user-level interrupt message indicative of a user-level interrupt to one or more recipients according to a user-level interrupt delivery configuration selected from a plurality of user-level interrupt delivery configurations. The one or more recipients correspond to one or more application threads executing on one or more processor cores of a plurality of processor cores in a multi-core system. A method includes generating an indicator of a user-level interrupt being undeliverable to one or more intended recipients of a user-level interrupt message according to a failed delivery notification mode configuration. The user-level interrupt may be issued by an application thread executing on a first processor core of a plurality of processor cores in a multi-core system. | 02-17-2011 |
| 20110208921 | INVERTED DEFAULT SEMANTICS FOR IN-SPECULATIVE-REGION MEMORY ACCESSES - A method for accessing memory by a first processor of a plurality of processors in a multi-processor system includes, responsive to a memory access instruction within a speculative region of a program, accessing contents of a memory location using a transactional memory access to the memory access instruction unless the memory access instruction indicates a non-transactional memory access. The method may include accessing contents of the memory location using a non-transactional memory access by the first processor according to the memory access instruction responsive to the instruction not being in the speculative region of the program. The method may include updating contents of the memory location responsive to the speculative region of the program executing successfully and the memory access instruction not being annotated to be a non-transactional memory access. | 08-25-2011 |
| 20110209151 | AUTOMATIC SUSPEND AND RESUME IN HARDWARE TRANSACTIONAL MEMORY - An apparatus and method is disclosed for a computer processor configured to access a memory shared by a plurality of processing cores and to execute a plurality of memory access operations in a transactional mode as a single atomic transaction and to suspend the transactional mode in response to determining an implicit suspend condition, such as a program control transfer. As part of executing the transaction, the processor marks data accessed by the speculative memory access operations as being speculative data. In response to determining a suspend condition (including by detecting a control transfer in an executing thread) the processor suspends the transactional mode of execution, which includes setting a suspend flag and suspending marking speculative data. If the processor later detects a resumption condition (e.g., a return control transfer corresponding to a return from the control transfer), the processor is configured to resume the marking of speculative data. | 08-25-2011 |
| 20110276972 | MEMORY-CONTROLLER-PARALLELISM-AWARE SCHEDULING FOR MULTIPLE MEMORY CONTROLLERS - Some embodiments of a processing system implement a memory-controller-parallelism-aware scheduling technique. In at least one embodiment of the invention, a method of operating a processing system includes scheduling a memory request requested by a thread of a plurality of threads executing on at least one processor according to thread priority information associated with the plurality of threads. The thread priority information is based on a maximum of a plurality of local memory bandwidth usage indicators for each thread of the plurality of threads. Each of the plurality of local memory bandwidth usage indicators for each thread corresponds to a respective memory controller of a plurality of memory controllers. | 11-10-2011 |
| 20110276973 | METHOD AND APPARATUS FOR SCHEDULING FOR MULTIPLE MEMORY CONTROLLERS - In at least one embodiment, a method includes locally scheduling a memory request requested by a thread of a plurality of threads executing on at least one processor. The memory request is locally scheduled according to a quality-of-service priority of the thread. The quality-of-service priority of the thread is based on a quality of service indicator for the thread and system-wide memory bandwidth usage information for the thread. In at least one embodiment, the method includes determining the system-wide memory bandwidth usage information for the thread based on local memory bandwidth usage information associated with the thread periodically collected from a plurality of memory controllers during a timeframe. In at least one embodiment, the method includes at each mini-timeframe of the timeframe accumulating the system-wide memory bandwidth usage information for the thread and updating the quality-of-service priority based on the accumulated system-wide memory bandwidth usage information for the thread. | 11-10-2011 |
| 20110276974 | SCHEDULING FOR MULTIPLE MEMORY CONTROLLERS - Some embodiments of a multi processor system implement a virtual-time-based quality-of-service scheduling technique. In at least one embodiment of the invention, a method includes scheduling a memory request to a memory from a memory request queue in response to expiration of a virtual finish time of the memory request. The virtual finish time is based on a share of system memory bandwidth associated with the memory request. The method includes scheduling the memory request to the memory from the memory request queue before the expiration of the virtual finish time of the memory request if a virtual finish time of each other memory request in the memory request queue has not expired and based on at least one other scheduling rule. | 11-10-2011 |
| 20110302586 | MULTITHREAD APPLICATION-AWARE MEMORY SCHEDULING SCHEME FOR MULTI-CORE PROCESSORS - A device may include a memory controller that identifies a multithread application, and adjusts a memory scheduling scheme for the multithread application based on the identification of the multithread application. | 12-08-2011 |
| 20110307689 | PROCESSOR SUPPORT FOR HARDWARE TRANSACTIONAL MEMORY - A processing core of a plurality of processing cores is configured to execute a speculative region of code as a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for an issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code. | 12-15-2011 |
| 20120036512 | ENHANCED SHORTEST-JOB-FIRST MEMORY REQUEST SCHEDULING - In at least one embodiment of the invention, a method includes scheduling a memory request associated with a thread executing on a processing system. The scheduling is based on a job length of the thread and a priority step function of job length. The thread is one of a plurality of threads executing on the processing system. In at least one embodiment of the method, the priority step function is a function of ┌x/2n┐ for x<=m and P(x)=m/2 | 02-09-2012 |
| 20120079491 | THREAD CRITICALITY PREDICTOR - Each thread of a multi-threaded application is assigned a ranking, referred to as thread criticality, based on the amount of time the thread is expected to take to complete one or more operations associated with the thread. More resources are assigned to threads having a higher thread criticality, in order to increase the rate at which the thread completes its operations. Thread criticality is determined using a perceptron model, whereby the thread criticality for a thread is a weighted sum of a set of data processing device performance characteristics associated with the thread, such as the number of instruction cache misses and data cache misses experienced by the thread. The weights of the perceptron model can be repeatedly adjusted over time based on repeated measurements that indicate the relative speed with which each thread is completing its operations. | 03-29-2012 |
| 20120124293 | PREVENTING UNINTENDED LOSS OF TRANSACTIONAL DATA IN HARDWARE TRANSACTIONAL MEMORY SYSTEMS - A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction. | 05-17-2012 |
| 20120124297 | COHERENCE DOMAIN SUPPORT FOR MULTI-TENANT ENVIRONMENT - A method includes bypassing a global coherence operation that maintains global memory coherence between a plurality of local memories associated with a plurality of corresponding processors. The bypassing is in response to an address of a memory request being associated with a local memory coherence domain. The method includes accessing a memory location associated with the local memory coherence domain according to the memory request in response to the address being associated with the local memory coherence domain. | 05-17-2012 |
| 20120124563 | COMPILER SUPPORT TECHNIQUE FOR HARDWARE TRANSACTIONAL MEMORY SYSTEMS - A method and apparatus for compiling software written to be executed on a microprocessor that supports at least one hardware transactional memory function is provided. A compiler that supports at least one software transactional memory function is adapted to include a runtime system that maps between the at least one software transactional memory function and the at least one hardware transactional memory instruction. | 05-17-2012 |
| 20120159084 | METHOD AND APPARATUS FOR REDUCING LIVELOCK IN A SHARED MEMORY SYSTEM - A method is provided for identifying a first portion of a computer program for speculative execution by a first processor element. At least one memory object is declared as being protected during the speculative execution. Thereafter, if a first signal is received indicating that the at least one protected memory object is to be accessed by a second processor element, then delivery of the first signal is delayed for a preselected duration of time to potentially allow the speculative execution to complete. The speculative execution of the first portion of the computer program may be aborted in response to receiving the delayed first signal before the speculative execution of the first portion of the computer program has been completed. | 06-21-2012 |
| 20120162237 | Bundle-Based CPU/GPU Memory Controller Coordination Mechanism - A system and method are disclosed for managing memory requests that are coordinated between a system memory controller and a graphics memory controller. Memory requests are pre-scheduled according to the optimization policies of the source memory controller and then sent over the CPU/GPU boundary in a bundle of pre-scheduled requests to the target memory controller. The target memory controller then processes pre-scheduling decisions contained in the pre-schedule requests, and in turn, issues memory requests as a proxy of the source memory controller. As a result, the target memory controller does not need to perform both CPU requests and GPU requests. | 06-28-2012 |
| 20120221785 | Polymorphic Stacked DRAM Memory Architecture - A 3D stacked processor device is described which includes a processor chip and a stacked polymorphic DRAM memory chip connected to the processor chip through a plurality of through-silicon-via structures, where the stacked DRAM memory chip includes a memory with an adjustable memory portion and an adjustable cache portion such that memory can operate simultaneously in both memory and cache modes. | 08-30-2012 |
| 20120233411 | Protecting Large Objects Within an Advanced Synchronization Facility - A system and method are disclosed for allowing protection of larger areas than memory lines by monitoring accessed and dirty bits in page tables. More specifically, in some embodiments, a second associative structure with a different granularity is provided to filter out a large percentage of false positives. By providing the associative structure with sufficient size, the structure exactly specifies a region in which conflicting cache lines lie. If entries within this region are evicted from the structure, enabling the tracking for the entire index filters out a substantial number of false positives (depending on a granularity and a number of indices present). In some embodiments, this associative structure is similar to a translation look aside buffer (TLB) with 4 k, 2M entries. | 09-13-2012 |
| 20120290793 | EFFICIENT TAG STORAGE FOR LARGE DATA CACHES - An apparatus, method, and medium are disclosed for implementing data caching in a computer system. The apparatus comprises a first data cache, a second data cache, and cache logic. The cache logic is configured to cache memory data in the first data cache. Caching the memory data in the first data cache comprises storing the memory data in the first data cache and storing in the second data cache, but not in the first data cache, tag data corresponding to the memory data. | 11-15-2012 |
| 20120297131 | Scheduling-Policy-Aware DRAM Page Management Mechanism - Memory controller page management devices, systems, and methods are disclosed in which a memory controller is configured to access memory in response to a memory access request by applying a scheduler-aware page management policy to at least one memory page based in the memory based on row buffer status information for the pending memory access requests scheduled in a current cycles. | 11-22-2012 |
| 20120311269 | NON-UNIFORM MEMORY-AWARE CACHE MANAGEMENT - An apparatus is disclosed for caching memory data in a computer system with multiple system memories. The apparatus comprises a data cache for caching memory data. The apparatus is configured to determine a retention priority for a cache block stored in the data cache. The retention priority is based on a performance characteristic of a system memory from which the cache block is cached. | 12-06-2012 |
| 20130013866 | SPATIAL LOCALITY MONITOR - A method includes updating a first tag access indicator of a storage structure. The tag access indicator indicates a number of accesses by a first thread executing on a processor to a memory resource for a portion of memory associated with a memory tag. The updating is in response to an access to the memory resource for a memory request associated with the first thread to the portion of memory associated with the memory tag. The method may include updating a first sum indicator of the storage structure indicating a sum of numbers of accesses to the memory resource being associated with a first access indicator of the storage structure for the first thread, the updating being in response to the access to the memory resource. | 01-10-2013 |
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| 20080317068 | SERVER-ASSISTED AND PEER-TO-PEER SYNCHRONIZATION - Systems and methods for synchronizing data between endpoints using elements of centralized and decentralized synchronization systems and communication topologies are disclosed. Such systems and methods may in some cases synchronize some subset of data with a centralized endpoint while another subset of data is synchronized in a decentralized fashion directly with other endpoints. Such systems and methods may include a variety of cooperative functionality to assist in the synchronization of data between endpoints. | 12-25-2008 |
| 20080320055 | Bi-Directional Data Modification With Synchronization - Systems and methods for synchronizing data between endpoints, including the modification of data on an endpoint without necessarily modifying data that is communicated between endpoints are disclosed. In such systems and methods the representation of data on an endpoint may be modified so that constraints on that particular endpoint are enforced, without requiring a similar or the same modification to the data when it is synchronized to other endpoints. | 12-25-2008 |
| 20100082534 | Method and System of Managing Conflicts for a Set of Synchronized Folders - Generally, the described system and process enables resolution of conflicts in a synchronized folder. Within the described mesh operating environment, each of the devices may be configured to do the same processing so that the file system view of the synchronized folder looks the same on all devices (pending local capabilities). Updates that cannot be immediately realized to the local store due to conflicts may be deferred for later attempts when, for example, additional updates at the system level or local level are made to resolve or eliminate the conflict for the update item. Generally, further changes may be propagated by a user in addressing a particular conflict that the user is notified about (e.g., via a selected winner that the user disagrees with). Alternatively, the conflict may resolve itself when a further update occurs that overrides or renders moot the previous update (e.g., a deleted item having a modified enclosure, where the enclosure had a previous concurrency conflict). | 04-01-2010 |
| 20110035355 | Bi-Directional Data Modification With Synchronization - Systems and methods for synchronizing data between endpoints, including the modification of data on an endpoint without necessarily modifying data that is communicated between endpoints are disclosed. In such systems and methods the representation of data on an endpoint may be modified so that constraints on that particular endpoint are enforced, without requiring a similar or the same modification to the data when it is synchronized to other endpoints. | 02-10-2011 |
| 20110173157 | Bi-Directional Data Modification With Synchronization - Systems and methods for synchronizing data between endpoints, including the modification of data on an endpoint without necessarily modifying data that is communicated between endpoints are disclosed. In such systems and methods the representation of data on an endpoint may be modified so that constraints on that particular endpoint are enforced, without requiring a similar or the same modification to the data when it is synchronized to other endpoints. | 07-14-2011 |
| 20120150801 | PLATFORM AGNOSTIC FILE ATTRIBUTE SYNCHRONIZATION - One or more techniques and/or systems are disclosed for providing platform agnostic synchronization for a custom functionality attribute of a file in a distributed data management system. An application and/or device may create or utilize a custom functionality attribute for a file in the distributed data management system. A custom attribute field, comprising data representative of the custom functionality attribute, can be attached to the file, such as with other metadata for the file. The custom attribute field can be stored with the file in the distributed data management system, and can remain unchanged and be synchronized with the file when the file is touched by a device on the distributed data management system. | 06-14-2012 |
| 20120210020 | SERVER-ASSISTED AND PEER-TO-PEER SYNCHRONIZATION - Systems and methods for synchronizing data between endpoints using elements of centralized and decentralized synchronization systems and communication topologies are disclosed. Such systems and methods may in some cases synchronize some subset of data with a centralized endpoint while another subset of data is synchronized in a decentralized fashion directly with other endpoints. Such systems and methods may include a variety of cooperative functionality to assist in the synchronization of data between endpoints. | 08-16-2012 |
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| 20100185687 | SELECTING ADVERTISEMENTS - An advertisement management system, a computer-implemented method, and computer readable media to select advertisements are provided. The advertisement management system includes a keyword component, a targeting component, and a merging component. The keyword component generates a lists of advertisements based on keywords provided by the advertisers. The targeting component, executing in parallel with the keyword component, generates another list of advertisements based on targeting data provided by the advertisers. The merging component combines the list of advertisements generated by the keyword component and targeting component based on relevance to user search terms received by the advertisement management system or revenue that the advertisement is able to generate for the advertiser, publisher, or advertisement management system. | 07-22-2010 |
| 20120084291 | APPLYING SEARCH QUERIES TO CONTENT SETS - Queries applied to content sets (e.g., files in a filesystem) often produce search results including many content items having identifiers that match the keywords of the query. However, many search techniques do not account for the relevance of the matching, e.g., whether the match is predictably relevant to the user, or whether the content item only tangentially matches the query. The techniques presented herein involve indexing the content items in a content index according to various identifiers having an identifier weight indicating the predicted relevance if a token of a query matches the identifier. Candidate content items may then be presented as search results sorted by the aggregated identifier weights of the matching identifiers, thereby promoting highly relevant content items and demoting incidentally matching content items. Additional adjustments may be made (e.g., promoting content items that match a particularly infrequent token or that match a phrase in the query). | 04-05-2012 |
| 20120084641 | SECURELY RENDERING ONLINE ADS IN A HOST PAGE - One or more techniques and/or systems are disclosed for rendering online ads on a webpage. A first inter-frame communication channel is created, which comprises a first communication channel between a first cross-domain frame and a host page, such as the webpage. The first cross-domain frame comprises content from a domain that is different than that of the host page domain. A second inter-frame communication channel is created comprising a second communication channel between the first cross-domain frame and a second cross-domain frame in the host page. | 04-05-2012 |
| 20120124143 | RICH EMAIL ATTACHMENT PRESENTATION - One or more techniques and/or systems are disclosed for providing a rich email experience for an email with an attachment. Intention metadata that is associated with an attachment to an email is identified, where the intention metadata indicates a sender intention for the attachment. The intention metadata may be identified prior to sending the email and included with the email, or identified after receipt of the email. Further, the intention metadata is applied to the attachment so that the attachment is presented in a rich format to the recipient that reflects the sender intention for the attachment, such as highlighting portions, and/or presenting images, for example, in a desired sequence. | 05-17-2012 |
| 20120130822 | COMPUTING COST PER INTERACTION FOR INTERACTIVE ADVERTISING SESSIONS - Described herein are technologies related to charging advertisers for advertisements presented to a user in an interactive advertising session. An advanced interactive system captures gestures, spoken words, facial expressions, and the like, and advertisements are presented to a user based upon such captured gestures, spoken words, facial expressions and the like. User interactions with respect to these advertisements are then captured, and advertisers are charged fees per captured interactions between the user and the advertisements. | 05-24-2012 |
| 20120143693 | Targeting Advertisements Based on Emotion - A computer system, a computer-implemented method, and computer readable media configured to target advertisements based on emotional states are provided. Advertisers specify desired emotional states of users they intend to target with advertisements. Advertisers also provide emotional tags having the desired emotional state of users that should see the advertisements linked to the emotional tags. Online activities for users are obtained and processed to assign emotional states to the users. An advertisement engine selects advertisements that are emotionally compatible based on the assigned emotional states and the desired emotional states provided by the advertisers. | 06-07-2012 |
| 20120150633 | GENERATING ADVERTISEMENTS DURING INTERACTIVE ADVERTISING SESSIONS - A method, computer readable media, and computer system for generating advertisement messages are provided. The computer system includes an advertisement engine and an advanced interactive platform that receive user events. The advanced interactive platform selects response templates associated with user events received from a user. In turn, the advanced interactive platform transmits the response templates to the advertisement engine. The advertisement engine processes the response template and populates the response template with advertising hints to dynamically generate advertisement messages. The advertisement engine may include indicators that solicit user feedback in the advertisement message. The user feedback received by the advanced interactive platform triggers additional user events that are used to generate additional advertisements and to discover interests of the user. | 06-14-2012 |
| 20120158502 | PRIORITIZING ADVERTISEMENTS BASED ON USER ENGAGEMENT - An advertisement engine, a computer-implemented method, and computer-readable media to select advertisements are provided. The advertisement engine is connected to an advertisement database and user database. The advertisement engine selects advertisements from the advertisement database based on user engagement data associated with a user. The user engagement data is stored in the user database. The user engagement data includes the length of time a user focused on content displayed by a client device. | 06-21-2012 |
| 20120159307 | RENDERING SOURCE REGIONS INTO TARGET REGIONS OF WEB PAGES - A target web page may embed resources hosted by a source server. However, this embedding may result in compatibility and/or security issues; e.g., the dimensions of the embedded resource may skew the layout of the target web page. Instead, a source web page may be rendered separately from a target web page, and a source region of the source web page (e.g., a region defined by a set of coordinates) may be extracted from the source web page and may be presented in a target region of the target web page. The elements of the source region may be displayed and executed in isolation within the source web page, and may operate within a source domain (e.g., communicating with the source server and accessing cookies stored by the source server), yet may not interact with the elements of the target web page, thereby alleviating many compatibility and security problems. | 06-21-2012 |
| 20120296742 | ADVERTISING UTILIZING DEVICE-TO-DEVICE INTERACTIONS - Methods and systems for enabling an advertiser to utilize device-to-device interactions to track word-of-mouth advertising and to take advantage of differentiated pricing schemes based on a quantity of an item are provided. An advertisement is received on a first device, and the first device identifies a second device that is receptive to interaction. The first device interacts with the second device. Concurrently with the interaction, an advertisement identifier associated with the advertisement is communicated from the first device to the second device. The advertisement identifier enables the second device to receive the advertisement. | 11-22-2012 |
| 20120303442 | ADVERTISEMENT RENDERING FOR MULTIPLE SYNCED DEVICES - Methods and systems for synchronizing communication of different versions of an advertisement to multiple, disparate devices associated with a user are provided. The advertisement is received on a first device associated with the user. Incident to receiving the advertisement, the first device establishes a communication path with a second device associated with the user. Utilizing the communication path, capabilities of the second device are determined. A version of the advertisement is rendered for the second device, where the version rendered is dependent upon the determined capabilities of the second device. And, utilizing the communication path, the rendered version of the advertisement is communicated to the second device. | 11-29-2012 |
