Patent application number | Description | Published |
20120326298 | BUMP STRUCTURE WITH BARRIER LAYER ON POST-PASSIVATION INTERCONNECT - A semiconductor device includes a barrier layer between a solder bump and a post-passivation interconnect (PPI) layer. The barrier layer is formed of at least one of an electroless nickel (Ni) layer, an electroless palladium (Pd) layer or an immersion gold (Au) layer. | 12-27-2012 |
20130034956 | CLEANING RESIDUAL MOLDING COMPOUND ON SOLDER BUMPS - A method of forming wafer-level chip scale packaging solder bumps on a wafer substrate involves cleaning the surface of the solder bumps using a laser to remove any residual molding compound from the surface of the solder bumps after the solder bumps are reflowed and a liquid molding compound is applied and cured. | 02-07-2013 |
20130093076 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - A method of a semiconductor package includes providing a substrate having a conductive trace coated with an organic solderability preservative (OSP) layer, removing the OSP layer from the conductive trace, and then coupling a chip to the substrate to form a semiconductor package. | 04-18-2013 |
20130099370 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The distance between the conductive pillar and the conductive trace is less than or equal to about 16 μm. | 04-25-2013 |
20130099371 | SEMICONDUCTOR PACKAGE HAVING SOLDER JOINTED REGION WITH CONTROLLED AG CONTENT - A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The silver (Ag) content in the solder layer is between 0.5 and 1.8 weight percent. | 04-25-2013 |
20130113094 | POST-PASSIVATION INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure. | 05-09-2013 |
20130143364 | METHOD OF PROCESSING SOLDER BUMP BY VACUUM ANNEALING - A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate. | 06-06-2013 |
20130187269 | PACKAGE ASSEMBLY AND METHOD OF FORMING THE SAME - A package assembly including a semiconductor die electrically coupled to a substrate by an interconnected joint structure. The semiconductor die includes a bump overlying a semiconductor substrate, and a molding compound layer overlying the semiconductor substrate and being in physical contact with a first portion of the bump. The substrate includes a no-flow underfill layer on a conductive region. A second portion of the bump is in physical contact with the no-flow underfill layer to form the interconnected joint structure. | 07-25-2013 |
20130244403 | METHOD AND DEVICE FOR CUTTING SEMICONDUCTOR WAFERS - A method for cutting a semiconductor wafer into semiconductor chips that reduces defects at the semiconductor chip corners. The method includes a pre-cutting processing step of trimming the semiconductor chip corners so that mechanical stress is reduced at the corners. The method includes dicing channels on a semiconductor wafer thereby defining the geometrical shape of one of the semiconductor chips, modifying the corners of the one of the semiconductor chips, and cutting the semiconductor wafer to separate the one of the semiconductor chips from other semiconductor chips. | 09-19-2013 |
20130248119 | APPARATUS AND METHOD OF SEPARATING WAFER FROM CARRIER - A method of separating a wafer from a carrier includes placing a wafer assembly on a platform. The wafer assembly includes the wafer, the carrier, and a layer of wax between the wafer and the carrier. A wafer frame is mounted on the wafer of the wafer assembly. The layer of wax is softened. The wafer and the wafer frame mounted thereon are separated, by a first robot arm, from the carrier. | 09-26-2013 |
20130260535 | METHOD AND APPARATUS FOR REDUCING PACKAGE WARPAGE - Embodiments of mechanisms for flattening a packaged structure are provided. The mechanisms involve a flattening apparatus and the utilization of protection layer(s) between the packaged structure and the surface(s) of the flattening apparatus. The protection layer(s) is made of a soft and non-sticking material to allow protecting exposed fragile elements of the packaged structure and easy separation after processing. The embodiments of flattening process involve flattening the warped packaged structure by pressure under elevated processing temperature. Processing under elevated temperature allows the package structure to be flattened within a reasonable processing time. | 10-03-2013 |
20130270700 | PACKAGE ON PACKAGE STRUCTURES AND METHODS FOR FORMING THE SAME - The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small. | 10-17-2013 |
20130273717 | Apparatus and Method for the Singulation of a Semiconductor Wafer - The present disclosure is directed to an apparatus for the singulation of a semiconductor substrate or wafer. In some embodiments the singulation apparatus comprises a plurality of cutting devices. The cutting devices are configured to form multiple concurrent cutting lines in parallel on a surface of the semiconductor wafer. In some embodiments, the singulation apparatus comprises at least two dicing saws or laser modules. The disclosed singulation apparatus can dice the semiconductor wafer into individual chips by dicing in a direction across a complete circumferential edge of the wafer, thereby decreasing process time and increasing throughput. | 10-17-2013 |
20130285238 | STUD BUMP STRUCTURE FOR SEMICONDUCTOR PACKAGE ASSEMBLIES - A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure. | 10-31-2013 |
20130307140 | PACKAGING WITH INTERPOSER FRAME - The mechanisms of using an interposer frame to package a semiconductor die enables fan-out structures and reduces form factor for the packaged semiconductor die. The mechanisms involve using a molding compound to attach the semiconductor die to the interposer frame and forming a redistribution layer on one or both sides of the semiconductor die. The redistribution layer(s) in the package enables fan-out connections and formation of external connection structures. Conductive columns in the interposer frame assist in thermal management. | 11-21-2013 |
20130309621 | METHOD AND APPARATUS FOR ADJUSTING WAFER WARPAGE - A method for adjusting the warpage of a wafer, includes providing a wafer having a center portion and edge portions and providing a holding table having a holding area thereon for holding the wafer. The wafer is placed onto the holding table with the center portion higher than the edge portions and thereafter pressed onto the holding area such that the wafer is attracted to and held onto the holding table by self-suction force. The wafer is heated at a predetermined temperature and for a predetermined time in accordance with an amount of warpage of the wafer in order to achieve a substantially flat wafer or a predetermined wafer level. | 11-21-2013 |
20140001652 | PACKAGE-ON-PACKAGE STRUCTURE HAVING POLYMER-BASED MATERIAL FOR WARPAGE CONTROL | 01-02-2014 |
20140008786 | BUMP-ON-TRACE PACKAGING STRUCTURE AND METHOD FOR FORMING THE SAME - A device comprises a first package component, and a first metal trace and a second metal trace on a top surface of the first package component. The device further includes a dielectric mask layer covering the top surface of the first package component, the first metal trace and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace. The device also includes a second package component and an interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, wherein the solder bump contacts the first metal trace in the opening of the dielectric mask layer. | 01-09-2014 |
20140045300 | WARPAGE CONTROL IN A PACKAGE-ON-PACKAGE STRUCTURE - The present disclosure relates to a tool arrangement and method to reduce warpage within a package-on-package semiconductor structure, while minimizing void formation within an electrically-insulating adhesive which couples the packages. A pressure generator and a variable frequency microwave source are coupled to a process chamber which encapsulates a package-on-package semiconductor structure. The package-on-package semiconductor structure is simultaneously heated by the variable frequency microwave source at variable frequency, variable temperature, and variable duration and exposed to an elevated pressure by the pressure generator. This combination for microwave heating and elevated pressure limits the amount of warpage introduced while preventing void formation within an electrically-insulating adhesive which couples the substrates of the package-on-package semiconductor structure. | 02-13-2014 |
20140048586 | Innovative Multi-Purpose Dipping Plate - The present disclosure is directed to an apparatus for the application of soldering flux to a semiconductor workpiece. In some embodiments the apparatus comprises a dipping plate having a reservoir which is adapted to containing different depths of flux material. In some embodiments, the reservoir comprises at least two landing regions having sidewalls which form first and second dipping zones. The disclosed apparatus can allow dipping of the semiconductor workpiece in different depths of soldering flux without the necessity for changing dipping plates. | 02-20-2014 |
20140117533 | Semiconductor Devices, Methods of Manufacture Thereof, and Packaged Semiconductor Devices - Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of contact pads over a substrate, and forming an insulating material over the plurality of contact pads and the substrate. The insulating material is patterned to form an opening over each of the plurality of contact pads, and the plurality of contact pads is cleaned. The method includes forming an under-ball metallization (UBM) structure over the plurality of contact pads and portions of the insulating material. Cleaning the plurality of contact pads recesses a top surface of each of the plurality of contact pads. | 05-01-2014 |
20140124955 | PACKAGE-ON-PACKAGE STRUCTURE INCLUDING A THERMAL ISOLATION MATERIAL AND METHOD OF FORMING THE SAME - A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component. | 05-08-2014 |
20140175548 | High Temperature Gate Replacement Process - A method for fabricating an integrated circuit device is disclosed. An exemplary method comprises performing a gate replacement process to form a gate structure, wherein the gate replacement process includes an annealing process; after the annealing process, removing portions of a dielectric material layer to form a contact opening, wherein a portion of the substrate is exposed; forming a silicide feature on the exposed portion of the substrate through the contact opening; and filling the contact opening to form a contact to the exposed portion of the substrate. | 06-26-2014 |
20140264930 | Fan-Out Interconnect Structure and Method for Forming Same - A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad. | 09-18-2014 |
20140273499 | Method and Apparatus for Localized and Controlled Removal of Material from a Substrate - A method and a system that include providing a localized dispensing apparatus. A substrate having a material disposed on its top surface is oriented above the localized dispensing apparatus. A chemical is then dispensed from the localized dispensing apparatus onto the top surface of the oriented substrate. The chemical removes the material. The path for the material removal may be determined and the localized dispensing apparatus programmed to provide chemical according to the path. | 09-18-2014 |
20140360671 | APPARATUS FOR SEPARATING WAFER FROM CARRIER - An apparatus for separating a wafer from a carrier includes a platform having an upper surface, a tape feeding unit, a first robot arm, and a controller coupled to the platform. The controller is configured to mount a wafer frame, by using the tape feeding unit, on a wafer of a wafer assembly on the upper surface of the platform. The wafer assembly includes the wafer, a carrier, and a layer of wax between the wafer and the carrier. The controller is also configured to heat the upper surface of the platform to a predetermined temperature and separate, by the first robot arm, the wafer and the wafer frame mounted thereon from the carrier. | 12-11-2014 |
20140370659 | SINGULATION APPARATUS AND METHOD - A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an adjacent singulation site. The carrier has a top surface configured to receive a semiconductor substrate thereon. Each of the plurality of singulation sites includes a deformable portion and at least one vacuum hole. The at least one vacuum hole and the deformable portion is configured to form a seal around the at least one vacuum holes when a force is applied. The present disclosure further includes a method of manufacturing semiconductor devices, especially for a singulation process. | 12-18-2014 |
20150021760 | MECHANISMS FOR FORMING BONDING STRUCTURES - Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar. | 01-22-2015 |
20150024606 | METHOD AND SYSTEM FOR THINNING WAFER THEREOF - Embodiments of a method for thinning a wafer are provided. The method includes placing a wafer on a support assembly and securing an etching mask to a backside of the wafer. The etching mask covers a peripheral portion of the wafer. The method further includes performing a wet etching process on the backside of the wafer to form a thinned wafer, and the thinned wafer includes peripheral portions having a first thickness and a central portion having a second thickness smaller than the first thickness. Embodiments of system for forming the thinned wafer are also provided. | 01-22-2015 |
20150061115 | INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF - A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b). | 03-05-2015 |
20150061162 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor structure includes several operations. The several operations include placing a plurality of dies on a carrier; defining a first zone and a second zone in a top surface of the carrier; calculating a first coverage ratio in the first zone; calculating a second coverage ratio in the second zone; disposing a dummy block on a specified location of the top surface of the carrier if the difference between the first coverage ratio and the second coverage ratio is greater than a predetermined value; forming a molding compound on the carrier. | 03-05-2015 |