Patent application number | Description | Published |
20080235417 | METHOD AND APPARATUS FOR BUS ENCODING AND DECODING - A method and an apparatus for bus encoding and a method and an apparatus for bus decoding are provided. The methods and apparatuses for bus encoding/decoding use a discontinuous pattern table (DPT) to store discontinuous pattern pairs. The tables are kept synchronous in both transmitter and receiver ends. After transmitting the first data in a discontinuous pattern pair, the second data may be transmitted by merely informing the receiver end through a control line instead of transmitting the second data by the bus. | 09-25-2008 |
20090160870 | RUN-TIME RECONFIGURABLE FABRIC FOR 3D TEXTURE FILTERING SYSTEM - The present invention discloses a texture filtering system, comprising a sequence generator, a retrieve unit and a dispatch unit. The sequence generator generates an execution sequence in each duty cycle. The execution sequence is the priority of respectively retrieving multiple pixels from multiple queues. The retrieve unit outputs multiple Boolean signals based on the limitation of the total number of all-purpose texture filters and the above priority in a duty cycle for determining from which queues the pixels are retrieved to perform a texture filtering process, and the dispatch unit assigns the multiple texture filter formats of the pixels to be processed and the anisotropic ratios thereof to multiple address generators. Besides, the present invention utilizes Brute force method to enable multiple bilinear texture filters to satisfy the various texture filter formats of a pixel, thereby markedly reducing the space occupied by the texture filter in a 3D graphic processing unit, provided that the specifications of the address generators and texture cache memory are unchanged. | 06-25-2009 |
20100049947 | PROCESSOR AND EARLY-LOAD METHOD THEREOF - A processor and an early-load method thereof are provided. In the early-load method, an instruction is fetched and determined in an instruction fetch stage to obtain a determination result. Whether to early-load an early-loaded data corresponding to the instruction is determined according to the determination result. A target data is fetched according to the instruction in an instruction execution stage if the early-loaded data is not loaded correctly. The early-loaded data is served as the target data if the early-loaded data is loaded correctly. | 02-25-2010 |
20100161951 | PROCESSOR AND METHOD FOR RECOVERING GLOBAL HISTORY SHIFT REGISTER AND RETURN ADDRESS STACK THEREOF - A method for recovering global history shift register (GHSR) and return address stack (RAS) is provided, which is applicable to an instruction pipeline of a processor and includes the following steps. First, provide a branch recovery table (BRT) and a backup stack. Whenever a branch instruction enters a predetermined stage of the instruction pipeline, add a record in the BRT according to the branch instruction. Whenever a return address is popped from the RAS of the instruction pipeline, push the return address into the backup stack. When flushing the instruction pipeline, determine a removal range of the BRT according to the condition which triggers the pipeline flush. Recover the RAS according to the records in the removal range and the backup stack. Remove all records in the removal range. Recover the GHSR of the instruction pipeline according to the removed records. | 06-24-2010 |
20100250850 | PROCESSOR AND METHOD FOR EXECUTING LOAD OPERATION AND STORE OPERATION THEREOF - A processor and a method for executing load operation and store operation thereof are provided. The processor includes a data cache and a store buffer. When executing a store operation, if the address of the store operation is the same as the address of an existing entry in the store buffer, the data of the store operation is merged into the existing entry. When executing a load operation, if there is a memory dependency between an existing entry in the store buffer and the load operation, and the existing entry includes the complete data required by the load operation, the complete data is provided by the existing entry alone. If the existing entry does not include the complete data, the complete data is generated by assembling the existing entry and a corresponding entry in the data cache. | 09-30-2010 |
20110197048 | DYNAMIC RECONFIGURABLE HETEROGENEOUS PROCESSOR ARCHITECTURE WITH LOAD BALANCING AND DYNAMIC ALLOCATION METHOD THEREOF - A dynamic reconfigurable heterogeneous processor architecture with load balancing and dynamic allocation method thereof is disclosed. The present invention uses a work control logic unit to detect load imbalance between different types of processors, and employs a number of dynamically reconfigurable heterogeneous processors to offload the heavier loaded processors. Hardware utilization of such design can be enhanced, and variation in computation needs among different computation phases can be better handled. To design the dynamic reconfigurable heterogeneous processors, a method of how to choose the basic building blocks and place the routing components is included. With the present invention, performance can be maximized at a minimal hardware cost. Hence the dynamic reconfigurable heterogeneous processor(s) so constructed and the load balancing and dynamic allocation method together will have the best performance at least cost. | 08-11-2011 |
20120290791 | PROCESSOR AND METHOD FOR EXECUTING LOAD OPERATION THEREOF - A processor and a method for executing load operation and store operation thereof are provided. The processor includes a data cache and a store buffer. When executing a store operation, if the address of the store operation is the same as the address of an existing entry in the store buffer, the data of the store operation is merged into the existing entry. When executing a load operation, if there is a memory dependency between an existing entry in the store buffer and the load operation, and the existing entry includes the complete data required by the load operation, the complete data is provided by the existing entry alone. If the existing entry does not include the complete data, the complete data is generated by assembling the existing entry and a corresponding entry in the data cache. | 11-15-2012 |
20140157285 | DYNAMIC RECONFIGURABLE HETEROGENEOUS PROCESSOR ARCHITECTURE WITH LOAD BALANCING AND DYNAMIC ALLOCATION METHOD THEREOF - A dynamic reconfigurable heterogeneous processor architecture with load balancing and dynamic allocation method thereof is disclosed. The present invention uses a work control logic unit to detect load imbalance between different types of processors, and employs a number of dynamic reconfigurable heterogeneous processors to offload the heavier loaded processors. Hardware utilization of such design can be enhanced, and variation in computation needs among different computation phases can be better handled. To design the dynamic reconfigurable heterogeneous processors, a method of how to choose the basic building blocks and place the routing components is included. With the present invention, performance can be maximized at a minimal hardware cost. Hence the dynamic reconfigurable heterogeneous processor(s) so constructed and the load balancing and dynamic allocation method together will have the best performance at least cost. | 06-05-2014 |