| Patent application number | Description | Published |
|---|
| 20080265302 | MEMORY STRUCTURE AND FABRICATING METHOD THEREOF - A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench. | 10-30-2008 |
| 20080283897 | FLASH MEMORY DEVICE AND FABRICATION METHOD THEREOF - The invention provides a flash memory device and a method for fabricating thereof. The device comprises a gate stack layer of a gate dielectric layer and a gate polysilicon layer formed on a substrate, a stack layer comprising a floating polysilicon layer and gate spacer formed on the sidewall of the gate stack layer. A metal layer is formed on the gate stack layer and is utilized in place of a portion of the gate polysilicon layer. Because the metal layer has relatively high conductivity and is electrically connected to a metal plug later formed, current velocity of the device is increased to improve performance. | 11-20-2008 |
| 20080296725 | SEMICONDUCTOR COMPONENT AND METHOD FOR FABRICATING THE SAME - A semiconductor component includes a substrate, two isolation structures, a conductor pattern and a dielectric layer. The isolation structures are disposed in the substrate, and each of the isolation structures has protruding portions protruding from the surface of the substrate. A trench is formed between the protruding portions. The included angle formed by the sidewall of the protruding portion and the surface of the substrate is an obtuse angle. The conductor pattern is disposed in the trench and fills the trench up. The dielectric layer is disposed between the conductor pattern and the substrate. | 12-04-2008 |
| 20090014886 | DYNAMIC RANDOM ACCESS MEMORY WITH AN ELECTROSTATIC DISCHARGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin. | 01-15-2009 |
| 20090047765 | METHOD OF MANUFACTURING NON-VOLATILE MEMORY - A method of manufacturing a non-volatile memory is provided. In the method, a first dielectric layer, a first conductive layer, and a first cap layer are formed sequentially on a substrate. The first cap layer and the first conductive layer are patterned to form first gate structures. A second dielectric layer is formed on the sidewall of the first gate structures, and a portion of the first dielectric layer is removed to expose the substrate between the first gate structures. An epitaxy layer is formed on the substrate between two first gate structures. A third dielectric layer is formed on the epitaxy layer. A second conductive layer is formed on the third dielectric layer. The first cap layer and a portion of the first conductive layer are removed to form second gate structures. Finally, a doped region is formed in the substrate at two sides of the second gate structures. | 02-19-2009 |
| 20090065846 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A manufacturing method of a non-volatile memory includes forming a first dielectric layer, a first conductive layer, and a first cap layer sequentially on a substrate to form first gate structures; conformally forming a second dielectric layer on the substrate; forming a first spacer having a larger wet etching rate than the second dielectric layer on each sidewall of each first gate structure; partially removing the first and second dielectric layers to expose the substrate. A third dielectric layer is formed on the substrate between the first gate structures; removing the first spacer; forming a second conductive layer on the third dielectric layer; removing the first cap layer and a portion of the first conductive layer to form second gate structures; and forming doped regions in the substrate at two sides of each second gate structure. | 03-12-2009 |
| 20090127610 | NON-VOLATILE MEMORY AND THE MANUFACTURING METHOD THEREOF - A non-volatile memory disposed on a substrate includes active regions, a memory array, and contacts. The active regions defined by isolation structures disposed in the substrate are extended in a first direction. The memory array is disposed on the substrate and includes memory cell columns, control gate lines and select gate lines. Each of the memory cell columns includes memory cells connected to one another in series and a source/drain region disposed in the substrate outside the memory cells. The contacts are disposed on the substrate at a side of the memory array and arranged along a second direction. The second direction crosses over the first direction. Each of the contacts extends across the isolation structures and connects the source/drain regions in the substrate at every two of the adjacent active regions. | 05-21-2009 |
| 20100279472 | MANUFACTURING METHOD OF NON-VOLATILE MEMORY - In a manufacturing method of a non-volatile memory, a substrate is provided, and strip-shaped isolation structures are formed in the substrate. A first memory array including memory cell columns is formed on the substrate. Each memory cell column includes memory cells connected in series with one another, a source/drain region disposed in the substrate outside the memory cells, select transistors disposed between the source/drain region and the memory cells, control gate lines extending across the memory cell columns and in a second direction, and first select gate lines respectively connecting the select transistors in the second direction in series. First contacts are formed on the substrate at a side of the first memory array and arranged along the second direction. Each first contact connects the source/drain regions in every two adjacent active regions. | 11-04-2010 |
| 20110065253 | MANUFACTURING METHOD FOR DOUBLE-SIDE CAPACITOR OF STACK DRAM - A manufacturing method for double-side capacitor of stack DRAM has steps of: forming a sacrificial structure in the isolating trench and the capacitor trenches; forming a first covering layer and a second covering layer on the sacrificial structure; modifying a part of the second covering layer; removing the un-modified second covering layer and the first covering layer to expose the sacrificial structure; removing the exposed part of the sacrificial structure to expose the electrode layer; removing the exposed electrode layer to expose the oxide layer; and removing the oxide layer and sacrificial structure to form the double-side capacitors. | 03-17-2011 |
| 20110081763 | PROCESS USING OXIDE SUPPORTER FOR MANUFACTURING A CAPACITOR LOWER ELECTRODE OF A MICRO STACKED DRAM - A process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM is disclosed. First, form a stacked structure. Second, form a photoresist layer on an upper oxide layer and then etch them. Third, deposit a polysilicon layer onto the upper oxide layer and the nitride layer. Fourth, deposit a nitrogen oxide layer on the polysilicon layer and the upper oxide layer. Sixth, partially etch the nitrogen oxide layer, the polysilicon layer and the upper oxide layer to form a plurality of vias. Seventh, oxidize the polysilicon layer to form a plurality of silicon dioxides surround the vias. Eighth, etch the nitride layer, the dielectric layer and the lower oxide layer beneath the vias. Ninth, form a metal plate and a capacitor lower electrode in each of the vias. Tenth, etch the nitrogen oxide layer, the polysilicon layer, the nitride layer and the dielectric layer. | 04-07-2011 |
| 20110084325 | DRAM STRUCTURE WITH A LOW PARASITIC CAPACITANCE AND METHOD OF MAKING THE SAME - An oxide spacer for stack DRAM gate stack is described, including: a semiconductor substrate with a memory array region and a periphery region, a plurality of gates disposed within the memory array region and the periphery region respectively, a silicon oxide spacer disposed on the gates, where the polysilicon contact plugs are formed by polysilicon deposition and chemical mechanical polish. After polysilicon contact plugs are formed, a silicon oxide layer is deposited to isolate the contacts and gate. The silicon oxide layer on top of contact plug is removed by chemical mechanical polish achieve planarization. | 04-14-2011 |
| 20110086490 | SINGLE-SIDE IMPLANTING PROCESS FOR CAPACITORS OF STACK DRAM - A single-side implanting process for capacitors of stack DRAM is disclosed. Firstly, form a stacked structure with a dielectric layer and an insulating nitride layer on a semi-conductor substrate and etch the stacked structure to form a plurality of trenches. Then, form conductive metal plates respectively on an upper surface of the stacked structure and bottoms of the trenches, form a continuous conductive nitride film, form a continuous oxide film, and form a photo resist layer for covering the trenches which are provided for isolation. Then, form a plurality of implanted oxide areas on a single-side surface, remove the photo resist layer, remove the plurality of implanted oxide areas, remove the conductive metal plates and the conductive nitride film uncovered by the oxide film, and remove the oxide film and the dielectric film. | 04-14-2011 |
| 20110090617 | CAPACITOR ELECTRODE, CAPACITOR STRUCTURE AND METHOD OF MAKING THE SAME - A method of fabricating a capacitor electrode. A stack structure is formed on a substrate, and the stack structure includes a first conductive layer, a first sacrificial layer, and a second sacrificial layer. The stack structure includes a first sidewall and a second sidewall facing the first sidewall. A conductive sidewall is formed on the first sidewall and the second sidewall to electrically connect the first conductive layer to the second conductive layer. Finally, the first and the second sacrificial layers are removed. | 04-21-2011 |
| 20110092044 | METHOD FOR MANUFACTURING CAPACITOR LOWER ELECTRODES OF SEMICONDUCTOR MEMORY - A method for manufacturing capacitor lower electrodes includes a dielectric layer, a first silicon nitride layer and a hard mask layer; partially etching the hard mask layer, the first silicon nitride layer and the dielectric layer to form a plurality of concave portions; depositing a second silicon nitride layer onto the hard mask layer and into the concave portions; partially etching the second silicon nitride layer, the hard mask layer and the dielectric layer to form a plurality of trenches; forming a capacitor lower electrode within each trench and partially etching the first silicon nitride layer, the second silicon nitride layer, the dielectric layer and the capacitor lower electrodes to form an etching area; and etching and removing the dielectric layer from the etching area, thereby a periphery of each capacitor lower electrode is surrounded and attached to by the second silicon nitride layer. | 04-21-2011 |
| 20110127574 | DEVICE FOR PREVENTING CURRENT-LEAKAGE - A device for preventing current-leakage is located between a transistor and a capacitor of a memory cell. The two terminals of the device for preventing current-leakage are respectively connected with a slave terminal of the transistor and an electric pole of the capacitor. The device for preventing current-leakage has at least two p-n junctions. The device for preventing current-leakage is a lateral silicon controlled rectifier, a diode for alternating current, or a silicon controlled rectifier. By utilizing the driving characteristic of the device for preventing current-leakage, electric charge stored in the capacitor hardly passes through the device for preventing current-leakage when the transistor is turned off to improve the current-leakage problem. | 06-02-2011 |
