Chung-Hsun
Chung-Hsun Huang, Fonghua Village TW
Patent application number | Description | Published |
---|---|---|
20080266461 | VIDEO PROCESSING CIRCUIT WITH MULTIPLE-INTERFACE - A video processing circuit with multiple-interface has a multiple-interface device, a timing controller, and a register. The timing controller is capable of sequencing and transmitting a signal of a low voltage differential signal, a reduced swing differential signal type or a transistor-transistor logic signal type to the multiple-interface device. The register sets the multiple-interface device to be adapted to output the signals of the types to a source driver. | 10-30-2008 |
Chung-Hsun Huang, Tainan City TW
Patent application number | Description | Published |
---|---|---|
20120105047 | PROGRAMMABLE LOW DROPOUT LINEAR REGULATOR - The present invention provides a programmable low dropout linear regulator using a reference voltage to convert an input voltage into a regulated voltage according to a control signal. The programmable low dropout linear regulator includes an operational amplifier having a negative input coupled to receive the reference voltage, a first transistor having a gate coupled to an output terminal of the operational amplifier and a first source/drain coupled to an output terminal of the regulated voltage, a first impedance coupled between a positive input of the operational amplifier and the output terminal of the regulated voltage, and a second impedance coupled between the positive input of the operational amplifier and a ground. The second impedance includes a second transistor having a gate coupled to receive the control signal. | 05-03-2012 |
Chung-Hsun Lee, Hsinchu City TW
Patent application number | Description | Published |
---|---|---|
20140032813 | METHOD OF ACCESSING A NON-VOLATILE MEMORY - A method of accessing a non-volatile memory is disclosed. Original bits of data are duplicated on a bit level to generate a plurality of duplicated bits corresponding to each original bit. At least one shielding bit is provided between the duplicated bits corresponding to different original bits. The duplicated bits and the at least one shielding bit are programmed to the non-volatile memory. The original bits are generated or determined according to the duplicated bits. | 01-30-2014 |
Chung-Hsun Lee, Chung Ho City TW
Patent application number | Description | Published |
---|---|---|
20110078541 | STORAGE DEVICE AND DATA PROCESS METHOD - A storage device and data processing method thereof is described. The invention provides different ECC for different memory pages. The storage device uses the long-bit ECC for easy interference page, and uses the short-bit ECC for hard interference page. Therefore, the accuracy of the data is maintained and the reading/writing speed is increased. | 03-31-2011 |
20110153961 | STORAGE DEVICE WITH FUNCTION OF VOLTAGE ABNORMAL PROTECTION AND OPERATION METHOD THEREOF - The present invention discloses a storage device and an operation method thereof. The storage device includes a non-volatile memory for storing data, a control unit coupled to the non-volatile memory, a power supply unit coupled to an external power source and converting the external power source to a suitable voltage for the non-volatile memory and the control unit, and a power monitor unit for monitoring the external power source. When the external power source falls below a low voltage threshold of the non-volatile memory, a control signal is transmitted into the control unit so as to stop accessing the non-volatile memory. The non-volatile memory finishes the last processing procedure according to the last programming instruction sent by the control unit before the control signal for protecting the data stored in the non-volatile memory. | 06-23-2011 |
Chung-Hsun Li, Xihu TW
Patent application number | Description | Published |
---|---|---|
20110273685 | PRODUCTION OF AN ALIGNMENT MARK - A method of production of alignment marks uses a self-aligned double patterning process. An alignment mark pattern is provided with first and second sub-segmented elements. After selecting the dipolar illumination orientation, dipole-X is used to illuminate the pattern and to image the first elements on the wafer, but not the second elements. Alternatively, dipole-Y is used to illuminate the pattern and to image the second elements on the wafer, but not the first elements. In either case, self-aligned double patterning processing may then be performed to produce product-like alignment marks with high contrast and wafer quality (WQ). Subsequently the X and Y alignment marks thus produced are used for the step of alignment in a lithographic process. | 11-10-2011 |
Chung-Hsun Lin, While Plains, NY US
Patent application number | Description | Published |
---|---|---|
20140306286 | TAPERED FIN FIELD EFFECT TRANSISTOR - A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor. | 10-16-2014 |
20140308806 | TAPERED FIN FIELD EFFECT TRANSISTOR - A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor. | 10-16-2014 |
Chung-Hsun Lin, Whitw Plains, NY US
Patent application number | Description | Published |
---|---|---|
20140048773 | Techniques for Metal Gate Work Function Engineering to Enable Multiple Threshold Voltage Nanowire FET Devices - A nanowire FET device includes a SOI wafer having a SOI layer over a BOX, and a plurality of nanowires and pads patterned in the SOI layer, wherein the nanowires are suspended over the BOX; an interfacial oxide surrounding each of the nanowires; and at least one gate stack surrounding each of the nanowires, the gate stack having (i) a conformal gate dielectric present on the interfacial oxide (ii) a conformal first gate material on the conformal gate dielectric (iii) a work function setting material on the conformal first gate material, and (iv) a second gate material on the work function setting material. A volume of the conformal first gate material and/or a volume of the work function setting material in the gate stack are/is proportional to a pitch of the nanowires. | 02-20-2014 |
Chung-Hsun Lin, Hopewell Junction, NY US
Patent application number | Description | Published |
---|---|---|
20140118059 | THROUGH-SUBSTRATE VIA SHIELDING - A semiconductor apparatus includes a substrate structure including a silicon substrate layer, a conductive through-substrate via extending through the silicon substrate layer. The apparatus further includes a semiconductor device located in the substrate structure and a conductive wall located between the through-substrate via and the semiconductor device. The conductive wall is in electrical contact with the silicon substrate layer. | 05-01-2014 |
20150035589 | THROUGH-SUBSTRATE VIA SHIELDING - A semiconductor apparatus includes a substrate structure including a silicon substrate layer, a conductive through-substrate via extending through the silicon substrate layer. The apparatus further includes a semiconductor device located in the substrate structure and a conductive wall located between the through-substrate via and the semiconductor device. The conductive wall is in electrical contact with the silicon substrate layer. | 02-05-2015 |
Chung-Hsun Wu, Tu-Cheng TW
Patent application number | Description | Published |
---|---|---|
20120187967 | VOLTAGE LIMITING TEST SYSTEM AND ASSISTANT TEST DEVICE - A voltage limiting test system used to test limit voltage values of a memory includes a voltage limiting test device and an assistant test device connected to the voltage limiting test device. The voltage limiting test device includes a button to adjust a voltage of the memory. The assistant test device includes a first timer, and first and second relays. The first relay is used to receive a state signal of the motherboard, to determine whether the first timer is powered according to the state signal. The second relay is used to receive the pulse signal output by the first timer when the first timer is powered, to trigger the button to adjust the voltage of the memory per a reference time. When the motherboard stops working, the voltage value of the memory is a limit voltage value of the memory. | 07-26-2012 |