| Patent application number | Description | Published |
|---|
| 20080205159 | VERIFICATION PROCESS OF A FLASH MEMORY - A verification process is disclosed for verifying correctness of a data status of a flash memory after data of the flash memory is altered. The flash memory has a plurality of memory cells array and a volatile memory. The verification process includes reading memory-cell verification data stored in the volatile memory, wherein the memory-cell verification data is for indicating a previous verification result of each memory cell is ‘success’ or ‘failure’; and performing a verification procedure on the memory cells failed in previous verification according to the memory-cell verification data, but not on the remained memory cells successful in previous verification. | 08-28-2008 |
| 20090019336 | MEMORY AND 1-BIT ERROR CHECKING METHOD THEREOF - A memory 1-bit error checking method is provided. Firstly, at least one piece of data fragment whose side is 2 | 01-15-2009 |
| 20090147591 | MEMORY CIRCUIT WITH HIGH READING SPEED AND LOW SWITCHING NOISE - A memory circuit with relatively high reading speed and relatively low switching noise is provided. The memory circuit includes an output buffer device having a first input receiving a data signal having a first voltage level, a second input receiving a pre-set voltage having a second voltage level and an output outputting the data signal, and a pre-set circuit constructed by a pair of MOSFETs and providing the pre-set voltage to the second input before the output buffer device receives the data signal. The pre-set circuit receives a control signal activating the pair of MOSFETs at the same time, and when the output buffer device receives the data signal, a voltage level of the second input is swung from the second level to the first voltage level. | 06-11-2009 |
| 20100046296 | METHOD FOR READING AND PROGRAMMING A MEMORY - A method for programming a memory is provided. The memory includes a number of cells and has a preset PV level for a target cell. The method includes programming a first-side of the target cell to have a Vt level not lower than the preset PV level; reading a Vt level of a second-side of the target cell and accordingly obtaining a corrected PV level corresponding to the first-side; and programming the first-side of the target cell to have a Vt level not lower than the corresponding corrected PV level. | 02-25-2010 |
| 20100074022 | MEMORY AND METHOD FOR PROGRAMMING THE SAME - A method for programming a memory is provided. The memory includes multiple rows of memory cells each including two half cells. The method includes the following steps. Whether the two half cells of a to-be-programmed memory cell of the n | 03-25-2010 |
| 20110069558 | LOCAL WORD LINE DRIVER OF A MEMORY - A memory includes a local word line driver for a memory array having a first word line and a second word line. The local word line driver includes a first selection transistor, a second selection transistor, and a middle transistor disposed between the first and second selection transistors. The first word line couples to the first selection transistor and the middle transistor, and the second word line couples to the middle transistor and the second selection transistor. | 03-24-2011 |
| 20110149671 | Operation Method and Leakage Controller for a Memory and a Memory Applying the Same - An operation method for a memory is provided. The operation method includes: starting a power on procedure on the memory; checking leakage for a bit line of the memory; and if the bit line has leakage, performing a leakage recovery on the bit line until the bit line passes the checking leakage step. | 06-23-2011 |
