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Chun-Yen
Chun-Yen Chang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090098714 | Method for forming III-nitrides semiconductor epilayer on the semiconductor substrate - GaN layer on semiconductor substrate is grown by using GaN nanorod buffer layer. Firstly, semiconductor substrate is cleaned and thermally degassed to remove the contaminant in the growth chamber. After the above step, the GaN nanorods layer is grown under the N-rich condition. Then, GaN epilayer is overgrown on the GaN nanorods layer under the Ga-rich condition for forming Group of III-Nitrides semiconductor layer on the semiconductor substrate. | 04-16-2009 |
| 20100197060 | Method of Forming Laterally Distributed LEDs - A method of forming laterally distributed light emitting diodes (LEDs) is disclosed. A first buffer layer with a first type of conductivity is formed on a semiconductor substrate, and a dielectric layer is formed on the first buffer layer. The dielectric layer is patterned to form a first patterned space therein, followed by forming a first active layer in the first patterned space. The dielectric layer is then patterned to form a second patterned space therein, followed by forming a second active layer in the second patterned space. Second buffer layers with a second type of conductivity are then formed on the first active layer and the second active layer. Finally, electrodes are formed on the second buffer layers and on the first buffer layer. | 08-05-2010 |
| 20110089467 | OHMIC CONTACT OF III-V SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - Heavily doped epitaxial SiGe material or epitaxial In | 04-21-2011 |
Chun-Yen Chang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090278165 | Light emitting device and fabrication method therefor - A light emitting device (LED) structure formed on a Group IV-based semiconductor substrate is provided. The LED structure includes a Group IV-based substrate, an AlN nucleation layer formed on the Group IV-based substrate, a GaN epitaxial layer formed on the AlN nucleation layer, a distributed Bragg reflector (DBR) multi-layer structure formed on the epitaxial layer, and an LED active layer formed on the DBR multi-layer structure. | 11-12-2009 |
| 20110197956 | THIN FILM SOLAR CELL WITH GRADED BANDGAP STRUCTURE - A thin film solar cell with a graded bandgap structure comprises a front contact, a first light absorption layer, a transition layer, a second light absorption layer and a back contact. The first light absorption layer is formed on the front contact, the transition layer is formed on the first light absorption layer, the second light absorption layer is formed on the transition layer, and the back contact is formed on the second light absorption layer, wherein the transition layer has a graded bandgap, which is made by alternating a layer of the first superlattice layers, having a first bandgap, with a layer of the second superlattice layers, having a second bandgap, in a tandem arrangement, based on the condition that the thickness of each layer of the first and the second superlattice layers is varied increasing, decreasing or increasing first and then decreasing. | 08-18-2011 |
Chun-Yen Chang, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090217379 | METHOD FOR ANTIVIRUS PROTECTION AND ELECTRONIC DEVICE WITH ANTIVIRUS PROTECTION - The invention provides a method for antivirus protection adapted for an electronic device. First, an option read only memory (ROM) is initialized. Second, all network connection ports of the electronic device are disabled. A first network connection port is enabled to connect the electronic device with an external system. Whether first antivirus software is installed on the electronic device is checked. If it is checked that the first antivirus software is not installed on the electronic device, after second antivirus software is received by the electronic device from the external system via the first network connection port and is installed on the electronic device, the electronic device enables all the network connection ports to connect the electronic device with the external system. | 08-27-2009 |
Chun-Yen Chang, Baoshan Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20110124139 | METHOD FOR MANUFACTURING FREE-STANDING SUBSTRATE AND FREE-STANDING LIGHT-EMITTING DEVICE - The present invention provides a method for manufacturing a free-standing substrate, comprising: growing a first layer having a sacrificial layer on a growth substrate; patterning the first layer into a patterned first layer having a structure of a plurality of protrusions; growing a second layer on the patterned first layer having a structure of a plurality of protrusions by epitaxial lateral overgrowth; and separating the second layer from the growth substrate by etching away the sacrificial layer, wherein the separated second layer functions as a free-standing substrate for epitaxy. Also, the present invention provides a method for manufacturing a free-standing light-emitting device, comprising: growing a first layer having a sacrificial layer on a growth substrate; patterning the first layer into a patterned first layer having a structure of a plurality of protrusions; growing a second layer on the patterned first layer having a structure of a plurality of protrusions by epitaxy growth; forming a reflecting layer on the second layer; forming a conductive substrate on the reflecting layer; and separating the second layer, the reflecting layer, and the conductive substrate from the growth substrate by etching away the sacrificial layer, so as to form a free-standing light-emitting device. | 05-26-2011 |
| 20110183480 | SEMICONDUCTOR DEVICE WITH GROUP III-V CHANNEL AND GROUP IV SOURCE-DRAIN AND METHOD FOR MANUFACTURING THE SAME - The present invention is related to a semiconductor device with group III-V channel and group IV source-drain and a method for manufacturing the same. Particularly, the energy level density and doping concentration of group III-V materials are increased by the heteroepitaxy of group III-V and group IV materials and the structural design of elements. The method comprises: preparing a substrate; depositing a dummy gate material layer on the substrate and defining a dummy gate from the dummy gate material layer by photolithography; performing doping by self-aligned ion implantation using the dummy gate as a mask and performing activation at high temperature, so as to form source-drain; removing the dummy gate; forming a recess in the substrate between the source-drain pair by etching; forming a channel-containing stacked element in the recess by epitaxy; and forming a gate on the channel-containing stacked element. | 07-28-2011 |
Chun-Yen Chang, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20120099240 | HIGH ENERGY DENSITY AND LOW LEAKAGE ELECTRONIC DEVICES - A magnetic capacitor includes two electrode layers, an insulator layer, and one or more magnetized layers. The insulator layer is located between the first electrode layer and the second electrode layer. The one or more magnetized layers include one or more ferro-magnetic elements that are magnetized. The one or more magnetized layers are located so that the one or more ferro-magnetic elements apply a magnetic field to the insulator layer to improve an electrical property of the insulator layer. Magnetic fields applied perpendicular to the electrode layers increase the capacitance and electrical energy storage of the insulator layer. Magnetic fields applied parallel to the electrode layers decrease the leakage current and increase the breakdown voltage of the insulator layer. The one or more ferro-magnetic elements used can include ferro-magnetic plates or magnetic nanodots. The one or more magnetized layers can be located between or outside of the electrode layers. | 04-26-2012 |
Chun-Yen Chen, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090162165 | SCREW FOR FASTENING WOODEN MATERIALS - A screw includes a shank portion including a tapered bottom section having a tip, a head on top of the shank portion, and first and second helical threads. The first helical thread extends helically around the shank portion in a first direction between the tip and the head, and has a first end distal from the head, and a second end opposite to the first end. The second helical thread extends helically around the shank portion in a second direction between the first helical thread and the tip, and has a third end proximate to the second end of the first helical thread. The first and second directions are opposite to each other. A non-helical ridge extends around the shank portion between the first and second helical threads. | 06-25-2009 |
| 20090257844 | Recessed head screw - A recessed head screw includes a head portion having a driver-engaging part between top and bottom faces thereof. The driver-engaging part includes a recess extending downwardly from the top face, four spaced-apart slanting walls slanting downwardly and convergingly from the top face, and four first bearing pieces each spacing two adjacent ones of the slanting walls and each having a four-sided first bearing face, and two substantially triangular second faces interconnected by the first bearing face. At least two second bearing pieces extend downwardly and respectively from bottoms of two opposite first bearing pieces. Each second bearing piece has a connecting face, and a third bearing face extending downwardly and inwardly from the connecting face. The connecting face inclines with respect to both of the third bearing face and the respective first bearing face. | 10-15-2009 |
Chun-Yen Chiu, Miao Li County TW
| Patent application number | Description | Published |
|---|---|---|
| 20110011717 | CAPACITIVE TOUCH CIRCUIT - A capacitive touch circuit includes a single comparator, a reference voltage control unit, a resistance adjusting unit, a delay unit, and a relaxation oscillation control unit. The comparator has a first input terminal, a second input terminal, and an output terminal. The reference voltage control unit is electrically connected to the second input terminal and includes a high level voltage source, a low level voltage source, and a voltage switching controller. The voltage switching controller electrically connects either the high level voltage source or the low level voltage source to the second input terminal of the single comparator according to an output signal of the single comparator. The relaxation oscillation control unit is electrically connected to the resistance adjusting unit, the delay unit, and the reference voltage control unit. The relaxation oscillation control unit outputs a relaxation oscillation signal, and the frequency of the relaxation oscillation signal varies according to the resistance set by the resistance adjusting unit. | 01-20-2011 |
Chun-Yen Huang, Taoyuan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100097596 | SCANNING EXPOSURE METHOD - A scanning exposure method is provided. A mask and a substrate are oppositely moved along a direction. The mask and the substrate are moved in at least two different uniform relative velocities during a one shot exposure, thus producing an exposed shot area of an expected size on the substrate. | 04-22-2010 |
| 20110059622 | SEMICONDUCTOR MANUFACTURING PROCESS - A semiconductor manufacturing process is provided. First, a wafer with a material layer and an exposed photoresist layer formed thereon is provided, wherein the wafer has a center area and an edge area. Thereafter, the property of the exposed photoresist layer is varied, so as to make a critical dimension of the exposed photoresist layer in the center area different from that of the same in the edge area. After the edge property of the exposed photoresist layer is varied, an etching process is performed to the wafer by using the exposed photoresist layer as a mask, so as to make a patterned material layer having a uniform critical dimension formed on the wafer. | 03-10-2011 |
Chun-Yen Huang, Beigang Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20120062212 | Zero Bias Power Detector - A zero bias power detector comprising a zero bias diode and an output boost circuit is provided. The output boost circuit comprises a zero bias transistor. The zero bias diode is not biased but outputs a rectifying signal according to a wireless signal. The zero bias transistor, not biased but coupled to the zero bias diode, is used for enhancing the rectifying signal. | 03-15-2012 |
Chun-Yen Hung, Hsichih TW
| Patent application number | Description | Published |
|---|---|---|
| 20100055224 | Suction Structure for a Mold - A suction structure for a mold includes a mold base, two airtight units, a plurality of air holes, and a plurality of air channels. The two airtight units are disposed in the mold base at interval and a suction zone is defined between the two airtight units. The plurality of air holes is located in the suction zone. The plurality of air channels is located in the suction zone and connected with the plurality of air holes. Based on the engagement of the suction zone, the plurality of air holes, and the plurality of air channels, a thin film can adhere to a mold via vacuum as air within the suction zone is extracted through the plurality of air holes. Thus, the thin film adheres to the mold fast and in a level manner, and thereby improving the yield rate of In-Mold Decoration process. | 03-04-2010 |
Chun-Yen Kuo, Pingtung County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100285558 | Apparatus and Method for High-Throughput Micro-Cell Culture with Mechanical Stimulation - A method for high-throughput micro-cell culture with mechanical stimulation includes providing cells on a membrane, supplying a culture medium to the cells, and vibrating the membrane by exerting and varying a fluid pressure on the membrane such that the cells are mechanically stimulated through the membrane. | 11-11-2010 |
Chun-Yen Lin, Taipei Hsien TW
| Patent application number | Description | Published |
|---|---|---|
| 20080216952 | Adhesive Method Of Optical Components - An adhesive method of adhering a first optical component to a second optical component includes applying a resin on a first predetermined area of the first optical component and a second predetermined area of the second optical component, and then arranging the first and second predetermined areas to correspond to each other, and then shortening the distance between the first and the second predetermined areas until a resin bridge being formed between the first and second optical components, and then lightly shortening the distance between the first and second predetermined areas for the resin being spread over the first and second predetermined areas, and then the resin being spread to be fully filled between the first and second optical components through the second optical component being released and pressing the resin, finally illuminating the resin through ultraviolet ray for engaging with the first and second optical components. | 09-11-2008 |
Chun-Yen Lin, Zhongli -City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110221405 | METHODS AND APPARATUS FOR CALIBRATION OF POWER CONVERTERS - Methods and apparatus for a power regulator according to various aspects of the present invention may comprise a sensor adapted to generate a measurement of a voltage or a current. A memory may store a correction parameter that corresponds to the measurement, and a correction system may be adapted to adjust the measurement according to the correction parameter. | 09-15-2011 |
Chun-Yen Lin, West Central Dist. TW
| Patent application number | Description | Published |
|---|---|---|
| 20110027615 | ELECTRODE STRUCTURE ADAPTED FOR HIGH APPLIED VOLTAGE AND FABRICATION METHOD THEREOF - An electrode structure adapted for high applied voltage is provided, which comprises a conductive plate substrate and a covering layer disposed thereon such that a covering percentage of the covering layer over the conductive plate substrate is more than 50%. Since area of the conductive plate substrate covered by the covering layer is larger than the area exposed, the possibility of arcing is reduced and the voltage applied to the electrode structure may be increased. | 02-03-2011 |
Chun-Yen Liu, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090215212 | Method for Fabricating A Flat Panel Display - The method for fabricating a flat panel display includes performing a first crystallization process to re-crystallize an amorphous silicon layer on a glass substrate to make the amorphous silicon layer become a polysilicon layer, forming a patterned absorbing layer to cover an active area pattern of a driving TFT and to expose portions of the polysilicon layer, performing a second crystallization process to re-crystallization the exposed portions of the polysilicon layer so that the exposed portions of the polysilicon layer has a different grain structure from the grain structure of the driving TFT, removing the patterned absorbing layer, and removing portions of the polysilicon layer to form an active area of the driving TFT and an active area of a switching TFT area in the exposed portions of the polysilicon layer of each sub-pixel. | 08-27-2009 |
Chun-Yen Yeh, Longtan Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20110024955 | Method of Fabricating Porous Soundproof Board - A porous soundproof board is fabricated Recycled waste, like slag, is used for fabrication. Slag and ceramics are mixed to be poured into a network foam carrier. Then, the soundproof board is fabricated through sintering. Thus the board fabricated has great added values and is environmental protected with low cost. | 02-03-2011 |