Patent application number | Description | Published |
20150248761 | PATTERN RECOGNITION BASED ON INFORMATION INTEGRATION - A method for recognizing a primitive in an image includes recognizing at least one primitive in the image to obtain at least one candidate shape of the at least one primitive, which at least one candidate shape has a respective confidence; determining whether the recognizing of the at least one primitive has a potential error based on the confidence; obtaining auxiliary information about the at least one primitive from a user in response to determining that the recognizing has the potential error; and re-recognizing the at least one primitive at least in part based on the auxiliary information. | 09-03-2015 |
20150294184 | PATTERN RECOGNITION BASED ON INFORMATION INTEGRATION - A method for recognizing a primitive in an image includes recognizing at least one primitive in the image to obtain at least one candidate shape of the at least one primitive, which at least one candidate shape has a respective confidence; determining whether the recognizing of the at least one primitive has a potential error based on the confidence; obtaining auxiliary information about the at least one primitive from a user in response to determining that the recognizing has the potential error; and re-recognizing the at least one primitive at least in part based on the auxiliary information. | 10-15-2015 |
20150319575 | TAGGING GEOGRAPHICAL AREAS - A method of tagging a geographical area includes obtaining, with a processing device, attribute information and mobile tracking data of a plurality of mobile objects, wherein the mobile tracking data comprises sampling time and corresponding sampling point locations of the mobile objects; converting the mobile tracking data of the plurality of mobile objects into new mobile tracking data according to the correspondence relationship between the sampling time and a time slices, wherein the new mobile tracking data include time slices and corresponding sampling point locations; and obtaining a set of attribute information of at least one geographical area with respect to the time slices based on the new mobile tracking data, wherein the at least one geographical area is obtained by clustering the sampling point locations. | 11-05-2015 |
20150319576 | TAGGING GEOGRAPHICAL AREAS - A method of tagging a geographical area includes obtaining, with a processing device, attribute information and mobile tracking data of a plurality of mobile objects, wherein the mobile tracking data comprises sampling time and corresponding sampling point locations of the mobile objects; converting the mobile tracking data of the plurality of mobile objects into new mobile tracking data according to the correspondence relationship between the sampling time and a time slices, wherein the new mobile tracking data include time slices and corresponding sampling point locations; and obtaining a set of attribute information of at least one geographical area with respect to the time slices based on the new mobile tracking data, wherein the at least one geographical area is obtained by clustering the sampling point locations. | 11-05-2015 |
20160034824 | AUTO-ANALYZING SPATIAL RELATIONSHIPS IN MULTI-SCALE SPATIAL DATASETS FOR SPATIO-TEMPORAL PREDICTION - A method and system to perform spatio-temporal prediction are described. The method includes obtaining, based on communication with one or more sources, multi-scale spatial datasets, each of the multi-scale spatial datasets providing a type of information at a corresponding granularity, at least two of the multi-scale spatial datasets providing at least two types of information at different corresponding granularities. The method also includes generating new features for each of the multi-scale spatial datasets, the new features being based on features of each of the multi-scale spatial datasets and spatial relationships between and within the multi-scale spatial datasets. The method further includes selecting, using the processor, features of interest from among the new features, training a predictive model based on the features of interest, and predicting an event based on the predictive model. | 02-04-2016 |
20160092770 | IDENTIFICATION OF TIME LAGGED INDICATORS FOR EVENTS WITH A WINDOW PERIOD - A method and system to identify a time lagged indicator of an event to be predicted are described. The method includes receiving information including an indication of a factor, the factor being a different event than the event to be predicted, and identifying a window period within which the event is statistically correlated with the factor. The method also includes collecting data for a duration of the window period, the data indicating occurrences of the factor and the event, and identifying a time lagged dependency of the event on the factor based on analyzing the data. | 03-31-2016 |
Patent application number | Description | Published |
20140244632 | Techniques For Ranking Character Searches - Techniques for asynchronous rendering are described. An apparatus may comprise a character set converter application, an index server, and a ranking application. The character set converter application may receive a search string comprised of one or more first character set characters, and convert the search string to one or more second character set characters that are different than the first character set. The index server may execute a search on the converted search string to obtain ranked individual search results. The ranking application may compare any first character set characters in the ranked individual search results to the first character set characters in the search string and sub-rank the ranked individual search results based on the strength of any matches. Other embodiments are described and claimed. | 08-28-2014 |
20150112977 | TECHNIQUES FOR RANKING CHARACTER SEARCHES - Techniques for asynchronous rendering are described. An apparatus may comprise a character set converter application, an index server, and a ranking application. The character set converter application may receive a search string comprised of one or more first character set characters, and convert the search string to one or more second character set characters that are different than the first character set. The index server may execute a search on the converted search string to obtain ranked individual search results. The ranking application may compare any first character set characters in the ranked individual search results to the first character set characters in the search string and sub-rank the ranked individual search results based on the strength of any matches. Other embodiments are described and claimed. | 04-23-2015 |
20160042067 | Blending Search Results on Online Social Networks - In one embodiment, a method includes receiving a search query from a user of an online social network and searching multiple verticals to identify multiple sets of objects in each vertical, respectively, that match the search query, and wherein each vertical stores one or more objects associated with the online social network. The method also includes ranking, for each set of identified objects from a vertical, each identified object in the set of identified objects. The method further includes blending the multiple sets of identified objects from each vertical to form a set of blended search results that includes a threshold number of identified objects, the blending including an iterative process performed at least the threshold number of iterations. Each iteration of the iterative blending process includes determining a blender score for each top-ranked identified object in each set of identified objects. | 02-11-2016 |
Patent application number | Description | Published |
20130334486 | STRUCTURE AND METHOD FOR A COMPLIMENTARY RESISTIVE SWITCHING RANDOM ACCESS MEMORY FOR HIGH DENSITY APPLICATION - The present disclosure provides a resistive random access memory (RRAM) structure. The RRAM structure includes a bottom electrode on a substrate; a resistive material layer on the bottom electrode, the resistive material layer including a defect engineering film; and a top electrode on the resistive material layer. | 12-19-2013 |
20130336041 | Structure and Method for a Forming Free Resistive Random Access Memory with Multi-Level Cell - The present disclosure provides one embodiment of a method for operating a multi-level resistive random access memory (RRAM) cell having a current-controlling device and a RRAM device connected together. The method is free of a “forming” step and includes setting the RRAM device to one of resistance levels by controlling the current-controlling device to one of current levels. The setting the RRAM device includes applying a first voltage to a top electrode of the RRAM device and applying a second voltage to a bottom electrode of the RRAM device. The second voltage is higher than the first voltage. | 12-19-2013 |
20140131794 | Innovative Approach of 4F Driver Formation for High-Density RRAM and MRAM - Some embodiments of the present disclosure relate to a vertical MOSFET selection transistor that is configured to suppress leakage voltage in the memory cell without limiting the size of the memory cell. The memory selection transistor has a semiconductor body with first and second trenches that define a raised semiconductor structure having a source region, a channel region, and a drain region. A gate structure has a first gate electrode in the first trench, which extends vertically along a first side of the raised semiconductor structure, and a second gate electrode in the second trench, which extends vertically along an opposite, second side of the raised semiconductor structure. The first and second gate electrodes collectively control the flow of current between the source and drain region in the raised semiconductor structure. An electrical contact couples the drain region to a data storage element configured to store data. | 05-15-2014 |
20140146593 | Method And Structure For Resistive Switching Random Access Memory With High Reliable And High Density - The present disclosure provides a resistive random access memory (RRAM) structure. The RRAM structure includes a bottom electrode on a substrate; a resistive material layer on the bottom electrode, the resistive material layer having filament features with a filament ratio greater than about 0.5; and a top electrode on the resistive material layer. | 05-29-2014 |
20140177318 | Hybrid Memory - A two-switch hybrid memory cell device includes a storage node connected between one terminal of a first switch and a gate of a second switch. The device also includes a resistive switching device connected to the storage node. The resistive switching device is to act as a capacitance by being set to a high resistive state when the memory cell is in a dynamic mode. | 06-26-2014 |
20140177330 | VERTICAL BJT FOR HIGH DENSITY MEMORY - Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively. | 06-26-2014 |
20140233294 | Memory Cell with Decoupled Read/Write Path - A memory cell with a decoupled read/write path includes a switch comprising a first terminal connected to a first line and a second terminal connected to a second line, a resistive switching device connected between a gate of the switch and a third line, and a conductive path between the gate of the switch and the second line. | 08-21-2014 |
20140241034 | Resistive Switching Random Access Memory Structure and Method To Recreate Filament and Recover Resistance Window - The present disclosure provides one embodiment of a method for operating a resistive random access memory (RRAM) cell. The method includes performing a forming operation to the RRAM cell with a forming voltage; performing a number of set/reset operation cycles to the RRAM cell; and performing a recreating process to the RRAM cell to recover RRAM resistance by applying a recreating voltage. Each of the number of set/reset operation cycles includes a set operation with a set voltage. The recreating voltage is greater than the set voltage. | 08-28-2014 |
20140339631 | Innovative Approach of 4F2 Driver Formation for High-Density RRAM and MRAM - Some embodiments of the present disclosure relate to a memory array comprising memory cells having vertical gate-all-around (GAA) selection transistors. In some embodiments, the memory array has a source region disposed within an upper surface of a semiconductor body, and a semiconductor pillar of semiconductor material extending outward from the upper surface of the semiconductor body and having a channel region and an overlying drain region. A gate region vertically overlies the source region at a position laterally separated from sidewalls of the channel region by a gate dielectric layer. A first metal contact couples the drain region to a data storage element that stores data. The vertical GAA selection transistors provide for good performance, while decreasing the size of the selection transistor relative to a planar MOSFET, so that the selection transistors do not negatively impact the size of the memory array. | 11-20-2014 |
20140361354 | Embedded Transistor - An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric. | 12-11-2014 |
20150085558 | DEVICE AND METHOD FOR FORMING RESISTIVE RANDOM ACCESS MEMORY CELL - A device and method for forming resistive random access memory cell are provided. The method includes: providing a first voltage to a first word line connected to a first RRAM cell to form the first RRAM cell; and providing a negative voltage to a second word line connected to a second RRAM cell that shares a first source line and a first bit line with the first RRAM cell. An exemplary device includes: a first RRAM cell, a second RRAM cell, a first voltage source and a charge pump circuit. The first RRAM cell is connected to a first word line. The second RRAM cell is connected to a second word line. The first voltage source provides a first voltage to the first word line to form the first RRAM cell. The charge pump circuit provides a negative voltage to the second word line. | 03-26-2015 |
20150109849 | DEVICE AND METHOD FOR SETTING RESISTIVE RANDOM ACCESS MEMORY CELL - A device and method for setting a resistive random access memory cell are provided. An exemplary method includes: providing a set current to a bit line of the RRAM cell by a current source. An exemplary device includes: a first RRAM cell and a current source. The first RRAM cell is connected to a first word line. The current source selectively connected to the first bit line. The current source selectively provides a current to the first bit line of the first RRAM cell to set the first RRAM cell. | 04-23-2015 |
20150187418 | Metal Line Connection for Improved RRAM Reliability, Semiconductor Arrangement Comprising the Same, and Manufacture Thereof - An integrated circuit device includes an array of RRAM cells, an array of bit lines for the array of RRAM cells, and an array of source lines for the array of RRAM cells. Both the source lines and the bit lines are in metal interconnect layers above the RRAM cells. The source line are thereby provided with a higher than conventional wire size, which increases the reset speed by approximately one order of magnitude. The lifetime of the RRAM transistors and the durability of the RRAM device are consequentially improved to a similar degree. | 07-02-2015 |
20150235698 | Method And Structure For Resistive Switching Random Access Memory With High Reliable And High Density - The present disclosure provides a resistive random access memory (RRAM) structure. The RRAM structure includes a bottom electrode on a substrate; a resistive material layer on the bottom electrode, the resistive material layer having filament features with a filament ratio greater than about 0.5; and a top electrode on the resistive material layer. | 08-20-2015 |
Patent application number | Description | Published |
20130140621 | FLASH MEMORY - A MONOS Charge-Trapping flash (CTF), with record thinnest 3.6 nm ENT trapping layer, has a large 3.1V 10-year extrapolated retention window at 125° C. and excellent 10 | 06-06-2013 |
20140349472 | FLASH MEMORY - A MONOS Charge-Trapping flash (CTF), with record thinnest 3.6 nm ENT trapping layer, has a large 3.1 V 10-year extrapolated retention window at 125° C. and excellent 10 | 11-27-2014 |
20150349086 | VERTICAL BJT FOR HIGH DENSITY MEMORY - Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively. | 12-03-2015 |
20160099291 | METAL LINE CONNECTION FOR IMPROVED RRAM RELIABILITY, SEMICONDUCTOR ARRANGEMENT COMPRISING THE SAME, AND MANUFACTURE THEREOF - Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area. | 04-07-2016 |