Patent application number | Description | Published |
20100164114 | Wire Structure of Semiconductor Device and Method for Manufacturing the Same - Disclosed herein are a wire structure of a semiconductor device and a method of making the same. The method includes obtaining a layout of an active region in a semiconductor substrate, the layout extending in a direction diagonally intersecting a layout of a bit line. The method also includes forming an isolation layer that delimits the active region, | 07-01-2010 |
20100327407 | INTERCONNECTION WIRING STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing an interconnection wiring structure of a semiconductor device includes forming an isolation region, which arranges active regions in a diagonal direction, in a semiconductor substrate; forming first damascene trenches, which open upper portions of a bit line contacts, by selectively etching a second interlayer insulation layer; forming bit lines which fill the first damascene trenches; forming second damascene trenches, which expose portions of the active region, by selectively etching the portion of a second interlayer insulation layer between the bit lines and the portion of the first interlayer insulation layer thereunder; attaching trench spacer on side walls of the second damascene trench; forming storage node contact lines which fill the second damascene trenches. | 12-30-2010 |
20100330791 | Method for Fabricating Contacts in Semiconductor Device - Disclosed is a method for fabricating a contact in a semiconductor device, including: obtaining a pattern layout including bit lines arranged across a cell matrix region of a semiconductor substrate, cell storage node contacts arranged to pass through a portion of a first interlayer insulation layer between the bit lines, and dummy storage node contacts additionally arranged in an end of the arrangement of the cell storage node contacts; and forming the cell storage node contacts and the dummy storage node contacts using the pattern layout. | 12-30-2010 |
20120175692 | Interconnection Wiring Structure of a Semiconductor Device - A method for manufacturing an interconnection wiring structure of a semiconductor device includes forming an isolation region, which arranges active regions in a diagonal direction, in a semiconductor substrate; forming first damascene trenches, which open upper portions of a bit line contacts, by selectively etching a second interlayer insulation layer; forming bit lines which fill the first damascene trenches; forming second damascene trenches, which expose portions of the active region, by selectively etching the portion of a second interlayer insulation layer between the bit lines and the portion of the first interlayer insulation layer thereunder; attaching trench spacer on side walls of the second damascene trench; and forming storage node contact lines which fill the second damascene trenches. | 07-12-2012 |
20120205733 | SEMICONDUCTOR DEVICE INCLUDING CAPACITOR AND DOUBLE-LAYER METAL CONTACT AND FABRICATION METHOD THEREOF - Disclosed are a semiconductor device comprising a capacitor and a double-layer metal contact and a method fabricating the same. The method comprising: forming a gate of a peripheral transistor for a peripheral circuit; forming a first contact and a first peripheral circuit wiring layer pattern on a first interlayer insulating layer; forming a second contact and a second peripheral circuit wiring layer pattern; selectively removing a portion of the second interlayer insulating layer in a cell region; forming a mold layer covering the second peripheral circuit wiring layer pattern; forming storage nodes passing through the mold layer; removing the mold layer; forming a dielectric layer and a plate node, which cover the storage nodes; forming a third interlayer insulating layer; and forming third contacts passing through the third interlayer insulating layer. | 08-16-2012 |
20120264274 | TRANSISTOR OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is a transistor of a semiconductor device and a method for fabricating the same. A transistor of a semiconductor device may include: a semiconductor substrate having an active region defined by an isolation layer; a recess trench formed in the active region and disposed to cross the semiconductor substrate in one direction; and a gate line formed in a straight line pattern, overlapping the recess trench and disposed to cross the recess trench at approximately right angles. | 10-18-2012 |
20130196477 | METHODS OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING FINE PATTERNS - Methods of fabricating a semiconductor device are provided. The method includes forming active lines in a semiconductor substrate, forming contact lines generally crossing over the active lines, forming line-shaped etch mask patterns generally crossing over the active lines and the contact lines, etching the contact lines exposed by the line-shaped etch mask patterns to form contact separation grooves and to form contact patterns generally remaining at intersections between the line-shaped etch mask patterns and the active lines, etching the active lines exposed by the contact separation grooves to form active separation grooves that generally divide each of the active lines into a plurality of active patterns, forming gates that substantially intersect the active patterns, and forming bit lines electrically connected to the contact patterns. | 08-01-2013 |
Patent application number | Description | Published |
20080296700 | METHOD OF FORMING GATE PATTERNS FOR PERIPHERAL CIRCUITRY AND SEMICONDUCTOR DEVICE MANUFACTURED THROUGH THE SAME METHOD - A method for forming gate patterns for a semiconductor device includes defining a cell array region and a peripheral region on a substrate. A layout is defined in a peripheral region. The layout comprises patterns having a plurality of fingers that extend along a first direction, wherein the fingers are spaced apart from adjacent fingers in a second direction at substantially the same interval, the patterns including gate patterns. | 12-04-2008 |
20090001482 | Transistor of Semiconductor Device and Method for Fabricating the Same - Provided is a transistor of a semiconductor device and a method for fabricating the same. A transistor of a semiconductor device may include: a semiconductor substrate having an active region defined by an isolation layer; a recess trench formed in the active region and disposed to cross the semiconductor substrate in one direction; and a gate line formed in a straight line pattern, overlapping the recess trench and disposed to cross the recess trench at approximately right angles. | 01-01-2009 |
20110159663 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING SPACER PATTERNING TECHNIQUE - A method for fabricating a semiconductor device using optical proximity correction to form high integrated cell patterns that are less prone to bridge defects. The method includes: obtaining a target layout of cell patterns, which form rows in a cell region, and peripheral patterns of a peripheral region; forming oblique patterns, which are alternately overlapped in the rows of the cell patterns, and a reverse pattern of the peripheral patterns; attaching spacers to sidewalls of the oblique patterns and the reverse pattern; forming first burying patterns between the oblique patterns and a second burying pattern around the reverse pattern by filling gaps between the spacers; and forming the cell patterns by cutting and dividing the middle portions of the oblique patterns and the first burying patterns, and setting the peripheral pattern with the second burying pattern by removing the reverse pattern. | 06-30-2011 |
Patent application number | Description | Published |
20080241384 | LATERAL FLOW DEPOSITION APPARATUS AND METHOD OF DEPOSITING FILM BY USING THE APPARATUS - A deposition apparatus and deposition method for forming a film on a substrate are disclosed. A film is deposited on a substrate by exposing the substrate to different flow directions of reactant gases. In one embodiment, the substrate is rotated in the reaction chamber after a film having an intermediate thickness is formed on the substrate. In other embodiments, the substrate is transferred from one reaction chamber to another after a film having an intermediate thickness is formed on the substrate. Accordingly, a film having a uniform thickness is deposited, averaging out depletion effect. | 10-02-2008 |
20090136665 | ATOMIC LAYER DEPOSITION APPARATUS - A reactor configured to subject a substrate to alternately repeated surface reactions of vapor-phase reactants is disclosed. In one embodiment, the reactor includes a reaction chamber that defines a reaction space; one or more inlets; an exhaust outlet; a gas flow control guide structure; and a substrate holder. The gas flow control guide includes one or more channels, each of which extends from a respective one of the one or more inlets to a first portion of a periphery of the reaction space. Each of the channels widens as the channel extends from the inlet to the reaction space. At least one of the channels is configured to generate a non-uniform laminar flow at the first portion of the periphery of the reaction space such that the laminar flow includes a plurality of flow paths that provide different amounts of a fluid. The reaction chamber may include a reactor base and a reactor cover detachable from each other; and a driver configured to independently adjust at least three portions of the reactor base to provide a substantially perfect seal to the reactor space. | 05-28-2009 |
20090156015 | DEPOSITION APPARATUS - A deposition apparatus configured to form a thin film on a substrate includes: a reactor wall; a substrate support positioned under the reactor wall; and a showerhead plate positioned above the substrate support. The showerhead plate defines a reaction space together with the substrate support. The apparatus also includes one or more gas conduits configured to open to a periphery of the reaction space at least while an inert gas is supplied therethrough. The one or more gas conduits are configured to supply the inert gas inwardly toward the periphery of the substrate support around the reaction space. This configuration prevents reactant gases from flowing between a substrate and the substrate support during a deposition process, thereby preventing deposition of an undesired thin film and impurity particles on the back side of the substrate. | 06-18-2009 |
20090163024 | METHODS OF DEPOSITING A RUTHENIUM FILM - A method of depositing includes: loading a substrate into a reactor; and conducting a plurality of atomic layer deposition cycles on the substrate in the reactor. At least one of the cycles includes steps of: supplying a ruthenium precursor to the reactor; supplying a purge gas to the reactor; and supplying non-plasma ammonia gas to the reactor after supplying the ruthenium precursor. The method allows formation of a ruthenium layer having an excellent step-coverage at a relatively low deposition temperature at a relatively high deposition rate. In situ isothermal deposition of barrier materials, such as TaN at 200-300° C., is also facilitated. | 06-25-2009 |
20120114856 | DEPOSITION APPARATUS - A deposition apparatus configured to form a thin film on a substrate includes: a reactor wall; a substrate support positioned under the reactor wall; and a showerhead plate positioned above the substrate support. The showerhead plate defines a reaction space together with the substrate support. The apparatus also includes one or more gas conduits configured to open to a periphery of the reaction space at least while an inert gas is supplied therethrough. The one or more gas conduits are configured to supply the inert gas inwardly toward the periphery of the substrate support around the reaction space. This configuration prevents reactant gases from flowing between a substrate and the substrate support during a deposition process, thereby preventing deposition of an undesired thin film and impurity particles on the back side of the substrate. | 05-10-2012 |