Patent application number | Description | Published |
20100061160 | DIE THERMAL SENSOR SUITABLE FOR AUTO SELF REFRESH, INTEGRATED CIRCUIT WITH THE SAME AND METHOD FOR ON DIE THERMAL SENSOR SUITABLE FOR AUTO SELF REFRESH - A semiconductor memory device includes a reference voltage generator for generating a plurality of reference voltages each having different voltage levels in response to a self refresh enable control signal, and a voltage comparator for generating a result signal that controls a self refresh operation cycle by comparing each of the plurality of reference voltages with a temperature information voltage that represents an internal temperature of an integrated circuit. | 03-11-2010 |
20100264960 | CIRCUIT FOR CHANGING FREQUENCY OF A SIGNAL AND FREQUENCY CHANGE METHOD THEREOF - A signal frequency change circuit is presented. The signal frequency change circuit includes a delay line, a detector, a controller, a multiplexer, and an output unit. The delay line delays a clock signal by a first delay time corresponding to a delay control signal to generate a delay signal and delays the clock signal by a second delay time shorter than a first delay time to generate a pre-frequency change clock signal. The detector generates a phase locked completion signal. The controller sequentially shifts the delay control signal and a multiplexing control signal. The multiplexer selects and outputs one of the pre-frequency change clock signals. The output unit generates a frequency change clock signal. | 10-21-2010 |
20100329040 | DATA ALIGNMENT CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS - A data alignment circuit of a semiconductor memory apparatus includes: a data strobe clock phase control block configured to control a phase of a data strobe clock signal in response to a strobe delay code and generate a delayed strobe clock signal; a plurality of data phase control blocks configured to control phases of input data in response to data delay codes and generate delayed data; a plurality of data alignment blocks configured to latch the delayed data in response to the delayed strobe clock signal and generate latched data and aligned data; and a delay code generation block configured to perform an operation of determining phases of the latched data and generate the strobe delay code and the data delay codes. | 12-30-2010 |
20110169552 | ON DIE THERMAL SENSOR SUITABLE FOR AUTO SELF REFRESH, INTEGRATED CIRCUIT WITH THE SAME AND METHOD FOR ON DIE THERMAL SENSOR SUITABLE FOR AUTO SELF REFRESH - A semiconductor memory device includes a reference voltage generator for generating a plurality of reference voltages each having different voltage levels in response to a self refresh enable control signal, and a voltage comparator for generating a result signal that controls a self refresh operation cycle by comparing each of the plurality of reference voltages with a temperature information voltage that represents an internal temperature of an integrated circuit. | 07-14-2011 |
20110242918 | GLOBAL LINE SHARING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE - A global line sharing circuit of a semiconductor memory device includes: a ZQ calibration unit configured to adjust an impedance of a DQ output driver; a test unit configured to control a test operation; and a shared global line coupled to and used in common by the ZQ calibration unit and the test unit. | 10-06-2011 |
20130021079 | SEMICONDUCTOR INTEGRATED CIRCUIT AND SIGNAL TRANSMISSION METHOD THEREOF - A semiconductor integrated circuit includes a plurality of semiconductor chips stacked in a multi-layer structure; a correction circuit in each semiconductor chip configured to reflect a delay time corresponding to the position of the chip in the stack into an input signal to output to each semiconductor chip; and a plurality of through-chip vias formed vertically through each of the semiconductor chips and configured to transmit the input signal to the semiconductor chip. | 01-24-2013 |
20140062612 | SIGNAL TRANSMISSION CIRCUIT HAVING CROSSTALK CANCELLATION UNIT - A signal transmission circuit may include a main driving unit configured to drive a first signal transmission line with given driving force in response to a first input signal, and a crosstalk cancellation unit configured to differentiate a signal transferred through a second signal transmission line, which is adjacent to the first signal transmission line, and incorporate a differentiated value into the first signal transmission line. | 03-06-2014 |
20140139269 | MULTI-CHIP SYSTEM AND SEMICONDUCTOR PACKAGE - A multi-chip system may include a plurality of chips, and a channel shared by the plurality of chips. At least one of the plurality of chips includes a transmission circuit configured to transmit a signal to the channel. Drivability of the transmission circuit is adjusted based on a number of the plurality of chips. | 05-22-2014 |
20140169112 | SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF - A semiconductor memory system configured to exchange signals through channels may include a memory control device configured to have a plurality of channels, a plurality of memory devices configured to be connected to each of the plurality of channels, wherein the plurality of channels share at least one of the plurality of memory devices. | 06-19-2014 |
20140176260 | SIGNAL TRANSMISSION CIRCUIT - A signal transmission circ it includes a main driving unit configured to drive a first signal transmission One in response to an input signal and output a first driven signal, an emphasis driving unit configured to perform an emphasis operation on the first driven signal and output an emphasized signal, and a crosstalk control unit configured to perform an equalizing operation on the emphasized signal. | 06-26-2014 |
20140306753 | MULTI-CHIP PACKAGE SYSTEM - A multi-chip package system includes a signal transmission line commonly coupled to a plurality of semiconductor chips to transfer data to/from the semiconductor chips from/to outside; and a termination controller suitable for detecting a loading value of the signal transmission line and controlling a termination operation on the signal transmission line based on the loading value. | 10-16-2014 |
20150061721 | SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of stacked chips, a reference through silicon via (TSV) set passing through the plurality of stacked chips, a plurality of TSVs passing through the plurality of stacked chips, a reference delay information generation unit suitable for generating a reference delay information indicating an amount of delay of the reference TSV set and a determination unit suitable for determining abnormality of the plurality of TSVs by comparing a first test signal with each of a plurality of second test signals, wherein the first test signal is an initial test signal delayed by an amount of delay corresponding to the reference delay information, and wherein each of the plurality of second test signals is the initial test signal delayed by corresponding one of the plurality of TSVs. | 03-05-2015 |