| Patent application number | Description | Published |
|---|
| 20100061160 | DIE THERMAL SENSOR SUITABLE FOR AUTO SELF REFRESH, INTEGRATED CIRCUIT WITH THE SAME AND METHOD FOR ON DIE THERMAL SENSOR SUITABLE FOR AUTO SELF REFRESH - A semiconductor memory device includes a reference voltage generator for generating a plurality of reference voltages each having different voltage levels in response to a self refresh enable control signal, and a voltage comparator for generating a result signal that controls a self refresh operation cycle by comparing each of the plurality of reference voltages with a temperature information voltage that represents an internal temperature of an integrated circuit. | 03-11-2010 |
| 20100264960 | CIRCUIT FOR CHANGING FREQUENCY OF A SIGNAL AND FREQUENCY CHANGE METHOD THEREOF - A signal frequency change circuit is presented. The signal frequency change circuit includes a delay line, a detector, a controller, a multiplexer, and an output unit. The delay line delays a clock signal by a first delay time corresponding to a delay control signal to generate a delay signal and delays the clock signal by a second delay time shorter than a first delay time to generate a pre-frequency change clock signal. The detector generates a phase locked completion signal. The controller sequentially shifts the delay control signal and a multiplexing control signal. The multiplexer selects and outputs one of the pre-frequency change clock signals. The output unit generates a frequency change clock signal. | 10-21-2010 |
| 20100329040 | DATA ALIGNMENT CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS - A data alignment circuit of a semiconductor memory apparatus includes: a data strobe clock phase control block configured to control a phase of a data strobe clock signal in response to a strobe delay code and generate a delayed strobe clock signal; a plurality of data phase control blocks configured to control phases of input data in response to data delay codes and generate delayed data; a plurality of data alignment blocks configured to latch the delayed data in response to the delayed strobe clock signal and generate latched data and aligned data; and a delay code generation block configured to perform an operation of determining phases of the latched data and generate the strobe delay code and the data delay codes. | 12-30-2010 |
