Patent application number | Description | Published |
20080240306 | CORRELATION DEVICE FOR PERFORMING CORRELATION ON A RECEIVED GLOBAL NAVIGATION SATELLITE SYSTEM SIGNAL AND METHOD FOR SAME - The invention provides a correlation device performing correlation on a received Global Navigation Satellite System (GNSS) signal. The correlation device comprises a first decimation module, a second decimation module, and a correlation module. The first decimation module decimates a plurality of samples of the received GNSS signal to obtain a plurality of decimated samples. The second decimation module decimates a plurality of code bits of a locally generated replica code to obtain a plurality of decimated code bits. The correlation module correlates the decimated samples with the decimated code bits to obtain a plurality of correlation results, thus achieving a coarse correlation between the received GNSS signal and the locally generated replica code. | 10-02-2008 |
20090041089 | SHARED CORRELATOR FOR SIGNALS WITH DIFFERENT CHIP RATES AND CORRELATION METHOD THEREOF - Disclosed is a shared correlator for processing signals with different chip rates from respective channels. The shared correlator comprises a mode controller, a plurality of sub-correlators, a PRN code generator and a plurality of accumulators. The mode controller arranges channel allocations for respective IF signals down converted from the signals. The PRN code generator generates respective PRN codes for the respective IF signals according to the respective chip rates thereof. The sub-correlators perform correlation to the respective IF signals with the respective PRN codes to obtain respective correlating results. The accumulators accumulate the respective correlation results to obtain respective overall correlation gains of the respective IF signals according to the respective chip rates. Each sub-correlator comprises a plurality of correlator cells, correlating one IF signal with one PRN code corresponding thereto according to the chip rate of the IF signal. | 02-12-2009 |
20090081978 | IF PROCESS ENGINE AND RECEIVER HAVING THE SAME AND METHOD FOR REMOVING IF CARRIERS USED THEREIN - A GNSS receiver having an IF process engine is disclosed. The IF process engine provides a plurality of carriers with different frequencies and down converts IF signals into baseband signals by using the carriers in a time division multiplex (TDM) schedule. The IF process engine has a local oscillator part for generating the carriers with different frequencies; an IF down-converter for respectively mixing the IF signal with the carriers generated by the local oscillator part to generate IF removed signal segments; a time division multiplex (TDM) controller for scheduling the respective mixing operations of the IF down-converter for the IF signal with the respective carriers; and a buffer for storing the IF removed signal segments generated by the IF down-converter. | 03-26-2009 |
20090106535 | SHARED PROCESSOR ARCHITECTURE APPLIED TO FUNCTIONAL STAGES CONFIGURED IN A RECEIVER SYSTEM FOR PROCESSING SIGNALS FROM DIFFERENT TRANSMITTER SYSTEMS AND METHOD THEREOF - According to an embodiment of the present invention, a shared processor architecture in a receiver system is disclosed. The receiver system is configured to have a first functional stage and a second functional stage for processing information carried by signals from a first transmitter system and a second transmitter system respectively. The first functional stage and the second functional stage correspond to an identical signal processing function. The shared processor architecture includes a first processor, allocated to the first functional stage and the second functional stage, for processing an output generated from the first functional stage or an output from the second functional stage. | 04-23-2009 |
20090195419 | MEMORY CODE GENERATOR - The invention provides a memory code generator. In one embodiment, the memory code generator comprises a code memory, a preparation buffer set, and a correlation buffer set. The code memory stores code data. The preparation buffer set retrieves a first code segment of the code data from the code memory, and shifts the first code segment to obtain a second code segment with a desired code phase required by the correlation buffer set. The correlation buffer set loads the second code segment from the preparation buffer set, and provides a correlation code for correlation according to the second code segment. The preparation buffer set prepares the second code segment corresponding to a subsequent correlation when the correlation buffer set is providing the correlation code for a current correlation according to the first code segment. | 08-06-2009 |
20090195450 | GNSS RECEIVER AND METHOD FOR GNSS MEMORY CODE GENERATION - The invention provides a Global Navigation Satellite System (GNSS) receiver. In one embodiment, the GNSS receiver comprises a memory, a buffer, a correlator, and a selector. The memory stores a memory code and outputs a portion of the memory code as a first code segment. The buffer comprises a plurality of component buffers and stores the first code segment into one of the component buffers in order. The selector selects a portion of the first code segments stored in the buffer as a second code segment output to the correlator according to the code phase selection signal, wherein the data length of the second code segment is equal to a correlation data length of the correlator. The correlator calculates a correlation between a received GNSS signal with the correlation data length and the second code segment. | 08-06-2009 |
20090198866 | CODE MEMORY CAPABLE OF CODE PROVISION FOR A PLURALITY OF PHYSICAL CHANNELS - The invention provides a code memory capable of code provision for a plurality of physical channels. In one embodiment, the code memory comprises a selecting multiplexer, a core memory module, and a code buffer. The selecting multiplexer repeatedly latches on to a plurality of addresses generated by the physical channels according to a sequence of the physical channels to generate a code memory address signal. The core memory module stores code data, and retrieves the code data according to the code memory address signal to generate a code memory data signal. The code buffer respectively retrieves a plurality of code segments requested by the physical channels from the code memory data signal according to the sequence of the physical channels, and stores the code segments. | 08-06-2009 |
20100097909 | METHOD AND APPARATUS FOR DETECTING SPECIFIC SIGNAL PATTERN IN A SIGNAL READ FROM AN OPTICAL DISC - A signal pattern detecting apparatus, which is capable of detecting a physical mark in a read back signal being read from an optical disc, includes a matching signal generator, a signal comparing device, and a decision circuit. The matching signal generator is utilized for generating a matching signal, capable of being utilized to identify the physical mark, according to a reference clock and a wobble clock. The signal comparing device is electrically connected to the matching signal generator, and utilized for comparing the matching signal with a wobble data signal to generate a comparison signal. The decision circuit is electrically connected to the signal comparing device, and utilized for generating an indication signal according to the comparison signal and a threshold value. Both the wobble data signal and the wobble clock are derived from the read back signal. | 04-22-2010 |
20100195746 | BOC SIGNAL ACQUISITION AND TRACKING METHOD AND APPARATUS - A BOC signal acquisition and tracking apparatus and method. In the present invention, at least a BOC signal, a BOC-cos signal and a PRN coded signal are generated for a received signal. Depending on application condition (e.g. acquisition mode or tracking mode), autocorrelation of the BOC signal is combined with cross-correlation of the BOC signal and one of the BOC-cos signal and the PRN coded signal to generate a proper combined correlation result. | 08-05-2010 |
20110243199 | GNSS Receiver and Method for GNSS Memory Code Generation - A GNSS receiver and method for GNSS memory code generation are disclosed. The GNSS receiver comprises a buffer, a correlator, and a selector. The buffer receives and stores a plurality of first code segments. Each of the first code segment is at least a portion of a memory code. The selector selects a selecting window of the first code segments stored in the buffer as a second code segment according to the code phase selection signal. The correlator calculates a correlation between a received GNSS signal and the second code segment. | 10-06-2011 |
20110248888 | SHARED MEMORY DEVICE APPLIED TO FUNCTIONAL STAGES CONFIGURED IN A RECEIVER SYSTEM FOR PROCESSING SIGNALS FROM DIFFERENT TRANSMITTER SYSTEMS AND METHOD THEREOF - A shared memory device for a receiver system is disclosed. The receiver system is configured to have a first functional stage and a second functional stage for processing information carried by signals transmitted from a first transmitter system through a first carrier frequency and a second transmitter system through a second carrier frequency respectively. The shared memory device has a memory space, allocated to be commonly shared by the first functional stage and the second functional stage, for buffering processing data generated from the first functional stage or the second functional stage. | 10-13-2011 |
20110291734 | CONFIGURABLE CALCULATING CIRCUIT AND RECEIVER HAVING A PLURALITY OF CONFIGURABLE CALCULATING CIRCUITS - A configurable calculating circuit includes a multiplexer, a mixer and an accumulator. The multiplexer is for receiving input signals including at least a first and a second input signals, and selectively outputting at least one of the input signals. The mixer is for mixing a selected input signal outputted from the multiplexer with a local oscillation signal to generate a mixed signal. The accumulator is for accumulating the mixed signal to generate an accumulated signal. When the configurable calculating circuit is operated under a first mode, the multiplexer selects the first input signal, and the accumulator performs a first accumulating operation upon the mixed signal; and when the configurable calculating circuit is operated under a second mode, the multiplexer selects the second input signal, and the accumulator performs a second accumulating operation, different from the first accumulating operation, upon the mixed signal. | 12-01-2011 |
20120014232 | DEVICE FOR ACCESSING ADDRESS INFORMATION IN AN OPTICAL DISC - An address-accessing device includes first and second information generators for producing first and second information according to the received address signals; a phase offset detector for producing a phase offset according to the first and second information; a reference signal generator for producing a reference signal according to the phase offset, the first information and the second information; and a decoder used to determine the structure type of an address-in-pregroove unit (ADIP) according to the reference value. This address-accessing device is capable of adjusting the decision level and the phase offset automatically to lower the error rate occurring in the address access procedure. | 01-19-2012 |
20120106685 | SIGNAL PROCESSING APPARATUS AND RELATED METHOD FOR GENERATING TARGET ESTIMATED SIGNAL OF SPECIFIC SIGNAL COMPONENT IN INPUT SIGNAL - A signal processing apparatus includes a signal generating block arranged to generate a target estimated signal of a specific signal component in an input signal. The signal generating block includes a reference signal generating circuit, a signal processing circuit, and a signal adjusting circuit. The reference signal generating circuit is arranged to generate a reference estimated signal for the specific signal component in the input signal. The signal processing circuit is coupled to the reference signal generating circuit, and arranged to process the reference estimated signal and accordingly generate a signal processing result. The signal adjusting circuit is coupled to the signal processing circuit and the reference signal generating circuit, and arranged to output the target estimated signal by adjusting the reference estimated signal according to the signal processing result. | 05-03-2012 |
20120146701 | CLOCK SYSTEM AND METHOD FOR COMPENSATING TIMING INFORMATION OF CLOCK SYSTEM - A clock system includes a clock signal generating circuit and a controlling circuit. The clock signal generating circuit is used for generating a primary clock signal and a reference clock signal both derived from an oscillating signal of the clock signal generating circuit. The controlling circuit is coupled to the clock signal generating circuit and used for receiving the primary clock signal under a normal mode and compensating timing information generated from the primary clock signal according to the reference clock signal when the clock system exits a power saving mode. The primary clock signal is de-activated when the clock system enters the power saving mode and is activated when the clock system exits the power saving mode. The clock system can keep a continue clock for system to use when the primary clock signal is gated or power saving mode is entered. | 06-14-2012 |