Patent application number | Description | Published |
20080248403 | METHOD AND SYSTEM FOR IMPROVING CRITICAL DIMENSION UNIFORMITY - A method for improving critical dimension uniformity of a wafer includes exposing a plurality of mask patterns on a first plurality of substrates at predetermined locations with common splits conditions of focus and exposure dose for each of the first plurality of substrates to form a plurality of perturbed wafers; measuring a critical dimension of the plurality of mask patterns at each of the predetermined locations for each of the plurality of perturbed wafers; averaging the critical dimension measured at each of the predetermined locations over the plurality of perturbed wafers to form a perturbed critical dimension map; measuring a sidewall angle of the plurality of mask patterns; averaging the sidewall angle measured to form a perturbed sidewall angle map; and providing the perturbed critical dimension map and the perturbed sidewall angle map to an exposure tool. | 10-09-2008 |
20090142701 | DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH - A method of lithography patterning includes forming a first resist pattern on a substrate, the first resist pattern including at least one opening therein on the substrate; curing the first resist pattern; forming a second resist pattern on the substrate; forming a material layer on the substrate; and removing the first and second resist patterns to expose the substrate. | 06-04-2009 |
20100201961 | System For Improving Critical Dimension Uniformity - A system for improving substrate critical dimension uniformity is described. The system includes an exposing means for exposing a plurality of mask patterns on a first plurality of substrates at predetermined locations with common splits of focus ({F | 08-12-2010 |
20110193202 | METHODS TO ACHIEVE 22 NANOMETER AND BEYOND WITH SINGLE EXPOSURE - Apparatus and methods are disclosed herein for fabricating semiconductor device features with a half-pitch node of 22 nm and beyond using single exposure and single etch (1P1E) photolithography techniques. The method includes exposing in a single exposure a photoresist layer to the exposure source through a photolithography mask where the photolithography mask has on it an island pattern of a material having high percentage transmission. The photoresist layer is developed using a negative tone developer to form a hole pattern in the photoresist layer. The 1P1E does not require the second photo exposure of the double patterning method. Furthermore, the method circumvents the island pattern collapsing issues and the need for strong illumination associated with exiting single 1P1E processes. | 08-11-2011 |
20110212403 | METHOD AND APPARATUS FOR ENHANCED DIPOLE LITHOGRAPHY - Provided is a lithography system that includes a source for providing energy, an imaging system configured to direct the energy onto a substrate to form an image thereon, and a diffractive optical element (DOE) incorporated with the imaging system, the DOE having a first dipole located in a first direction and a second dipole located in the first direction or a second direction perpendicular the first direction. The first dipole includes a first energy-transmitting region spaced a first distance from a center of the DOE. The second dipole includes a second energy-transmitting region spaced a second distance from the center of the DOE. The first distance is greater than the second distance. | 09-01-2011 |
20110284966 | Structure and Method for Alignment Marks - The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant. | 11-24-2011 |
20110285036 | OVERLAY MARK ASSISTANT FEATURE - A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector. | 11-24-2011 |
20110294286 | REVERSE PLANARIZATION METHOD - A method for fabricating an integrated circuit device is disclosed. The method includes providing a substrate; forming a semiconductor feature over the substrate; forming a first photoresist layer over the substrate; performing a lithography process on the first photoresist layer, such the first photoresist layer includes an opening therein that exposes the semiconductor feature; performing a stabilization process on the first photoresist layer; forming a second photoresist layer over the first photoresist layer, wherein the second photoresist layer fills the opening; and etching back the first and second photoresist layers until the semiconductor feature is exposed. | 12-01-2011 |
20130330904 | OVERLAY MARK ASSISTANT FEATURE - A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector. | 12-12-2013 |
20140272714 | DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a first resist pattern on a substrate, wherein the first resist pattern including a plurality of openings. A second resist pattern is formed on the substrate and within the plurality of openings of the first resist pattern, wherein the second resist pattern includes at least one opening therein on the substrate. The first resist pattern is removed to uncover the substrate underlying the first resist pattern. | 09-18-2014 |