| Patent application number | Description | Published |
|---|
| 20110059407 | DOUBLE PATTERNING STRATEGY FOR FORMING FINE PATTERNS IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a first resist pattern over a substrate, baking the first resist features, hardening the first resist features, forming a second resist layer within the hardened first resist features, and patterning the second resist layer to form at least one second resist feature between the hardened first features. | 03-10-2011 |
| 20110171795 | FinFET LDD and Source Drain Implant Technique - A method of forming an integrated circuit includes providing a semiconductor wafer; and forming a fin field-effect transistor (FinFET) including implanting the semiconductor wafer using a hot-implantation to form an implanted region in the FinFET. The implanted region comprises a region selected from the group consisting essentially of a lightly doped source and drain region, a pocket region, and a deep source drain region. | 07-14-2011 |
| 20110195555 | Techniques for FinFET Doping - A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer. | 08-11-2011 |
| 20110212592 | METHOD OF FORMING ULTRA-SHALLOW JUNCTIONS IN SEMICONDUCTOR DEVICES - A method of forming MOS transistor includes the steps of performing a pocket implantation process on a substrate having a gate stack, performing a co-implanted ion implantation process on the substrate at a temperature less than room temperature, performing a lightly doped source/drain implantation process on the substrate, and forming source and drain regions in the substrate, adjacent the gate stack. | 09-01-2011 |
| 20110269287 | METHODS FOR DOPING FIN FIELD-EFFECT TRANSISTORS - An embodiment of the disclosure includes doping a FinFET. A dopant-rich layer comprising an dopant is formed on a top surface and sidewalls of a semiconductor fin of a substrate. A cap layer is formed to cover the dopant-rich layer. The substrate is annealed to drives the dopant from the dopant-rich layer into the semiconductor fin. | 11-03-2011 |
| 20110295539 | METHOD AND APPARATUS FOR MEASURING INTRA-DIE TEMPERATURE - A method for measuring the intra-die temperature of a wafer with a fast response time is described. The method includes providing a wafer in a thermal process chamber, radiating the wafer in a first predetermined radiation range to heat the wafer to a predetermined temperature range for a predetermined time, receiving the radiation reflected from a die area while the wafer is being heated and detecting reflected radiation having a second predetermined radiation range, and determining a temperature of the die area by a processor being responsive to the detected second predetermined radiation range. | 12-01-2011 |
| 20120015459 | Thermal Leveling for Semiconductor Devices - A semiconductor device and a method of manufacturing are provided. In some embodiments, a backside annealing process such that a first heat source is placed along a backside of the substrate. In other embodiments, the first heat source is used in combination with an anti-reflection dielectric (ARD) layer is deposited over the substrate. In yet other embodiments, a second heat source is placed along a front side of the substrate in addition to the first heat source placed on the backside of the substrate. In yet other embodiments, a heat shield may be placed between the substrate and the second heat source on the front side of the substrate. In yet further embodiments, a single heat source may be used on the front side of the substrate in combination with the ARD layer. A reflectivity scan may be performed to determine which anneal stage (RTA or MSA or both) to place thermal leveling solution. | 01-19-2012 |
| 20120018848 | HIGH SURFACE DOPANT CONCENTRATION SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING - The present disclosure provides a high surface dopant concentration semiconductor device and method of fabricating. In an embodiment, a method of forming the semiconductor device includes providing a substrate, forming a doped region in the substrate, forming a stressing layer over the doped region, performing a boron (B) doping implant to the stressing layer, annealing the B doping implant, and after annealing the B doping implant, forming a silicide layer over the stressing layer. | 01-26-2012 |
