Patent application number | Description | Published |
20090284909 | FLAT PANEL DISPLAY AND CHIP BONDING PAD - A flat panel display and a chip bonding pad thereof are provided. The flat panel display includes a display panel, an FPC board, first and second source driving chips, and a control circuit board. First and second wires in a peripheral circuit region of the display panel extend from the underneath of the FPC board to two opposite sides of the display panel and electrically connect the FPC board. The first source driving chips electrically connect the FPC board through parts of the first wires. The second source driving chips electrically connect the FPC board through the second wires. The chip bonding pad is under one of the first and second source driving chips. The chip bonding pad includes a first dielectric layer having first through holes and a second dielectric layer having second and third through holes arranged alternately. The second through holes correspond to the first through holes. | 11-19-2009 |
20100315401 | Driver Circuit Structure and Method for Repairing the Same - Disclosed is a driver circuit structure integrated in a display panel. The driver circuit structure includes a plurality of transistors and a backup transistor. After completing the driver circuit structure, the disclosure inspects it to find an inactive transistor. The inspection process first, isolates the electrical connection between the inactive transistor and the first electrode line and/or the electrical connection between the inactive transistor and the second electrode line. Next, the source electrode of the backup transistor and the first electrode line and/or electrically connecting the drain electrode of the backup transistor and the second electrode line are electrical connected. | 12-16-2010 |
20110002437 | SHIFT REGISTERS - A shift register is provided and includes a first shift registering unit and a second shift registering unit. The first shift registering unit generates a first trigger signal at a first output terminal and includes a first pull-down circuit. The second shift registering unit receives the first trigger signal and generates a second trigger signal at a second output terminal. The first trigger signal and the second trigger signal are sequentially asserted. The second shift registering unit includes a second pull-down circuit. The first pull-down circuit and the second pull-down circuit perform pull-down operations at different times. When the first pull-down circuit does not perform the pull-down operation, the second pull-down circuit performs pull-down operations to the first output terminal. | 01-06-2011 |
20110205461 | LCD display visual enhancement driving circuit and method - A pixel in a liquid crystal display panel comprises a first sub-pixel area having a first sub-pixel electrode and a second sub-pixel area having a second sub-pixel electrode. Each sub-pixel electrode is associated with a capacitor. When a gate-line signal and a data voltage is provided to the pixel, the voltage level on the first sub-pixel electrode is substantially equal to or slightly higher than the voltage level on the second sub-pixel electrode and the capacitor associated with each sub-pixel electrode is charged. When the gate-line signal has entirely passed on partially passed, a circuit element causes the capacitor associated with the second sub-pixel electrode to transfer its charge to another capacitor, resulting in a reduction of the voltage level on the second sub-pixel electrode. | 08-25-2011 |
20110316833 | Shift Register and Architecture of Same on a Display Panel - The present invention relates to a shift register and GOA architecture of the same in a display panel comprising a substrate and a plurality of pixels spatially formed on the substrate defining a number of pixel rows, each pixel row having a height of H. The shift register has the plurality of shift register stages disposed spatially and sequentially on the substrate in such a way that the layout of each shift register stage has a height of (j*H), j being an integer greater than one. Each shift register stages is configured to generate j scanning signals for driving j neighboring pixel rows, respectively. | 12-29-2011 |
20130278567 | BUS-LINE ARRANGEMENT IN A GATE DRIVER - A method for use in a display panel is disclosed. The method includes providing M bus lines in the bus area for receiving a plurality of clock signals, M being a positive integer greater than 3; providing a plurality of signal lines to separately provide the clock signals from the M bus line to the circuit area, the circuit area configured to provide the plurality of sequential gate line signals in response to the clock signals, the plurality of signal lines including a plurality of adjacent signal-line pairs, each adjacent signal-line pair having a resistance difference, said signal lines including a maximum resistance value and a minimum resistance value, and wherein the M bus lines are arranged such that the resistance difference in any one of the adjacent signal-line pairs is smaller than a value difference between the maximum resistance value and the minimum resistance value. | 10-24-2013 |
20130280822 | METHOD FOR REPAIRING DRIVER CIRCUIT STRUCTURE - Disclosed is a driver circuit structure integrated in a display panel. The driver circuit structure includes a plurality of transistors and a backup transistor. After completing the driver circuit structure, the disclosure inspects it to find an inactive transistor. The inspection process first, isolates the electrical connection between the inactive transistor and the first electrode line and/or the electrical connection between the inactive transistor and the second electrode line. Next, the source electrode of the backup transistor and the first electrode line and/or electrically connecting the drain electrode of the backup transistor and the second electrode line are electrical connected. | 10-24-2013 |
Patent application number | Description | Published |
20080232632 | Ear hooked earphone - An ear hooked earphone is provided for selectively being worn on a left or right ear of a user. The earphone includes a body and an ear hook. The body includes a first coupled portion formed on a surface thereof. The ear hook includes a hook section and a fastened section. The hook section is used for hooking around the ear of the user. The fastened section is connected with the hook section, and a separation is formed between ends of the hook section and the fastened section. The fastened section has a second coupled portion, and one of two sides of the second coupled portion is selectively coupled with the first coupled section. Thereby, the position of the separation relative to the body is able to be changed, that is, the ear hooked earphone is able to hang on the left or right ear of the user freely. | 09-25-2008 |
20080247589 | Earplug Earphone - An earplug earphone with a special engagement is provided. The earplug earphone includes a body and an earplug. The body has a protruding connecting portion, wherein the protruding connecting portion has a first engaging element on the inner side thereof. The earplug includes a protruding portion having a second engaging element. The earplug is fixed to the body by engagement of the engaging elements. After the protruding connecting portion is combined with the protruding portion, a buffering segment spaced apart in an appropriate distance is formed between the earplug and the body. The buffering segment has an advantage for the earplug to match different external auricles of different users and to be inserted in the ears of different users, thereby making the earplug earphone of the present invention further conform to ergonomics. | 10-09-2008 |
20090041288 | EAR-LOOP EARPHONE - An ear-loop earphone includes a main body having a surrounding side, an ear-loop base, and an ear-loop. The ear-loop base, fixed on the surrounding side of the main body in a rotatable manner, is capable of rotating around a first axis. The ear-loop, fixed on the ear-loop base in a rotatable manner, capable of rotating around a second axis different from the first axis. | 02-12-2009 |
20090097690 | ADJUSTABLE EARPHONE - An earphone includes a body with a surrounding side, a rotatable loop and an ear hook. The rotatable loop is pivotally connected with the body on two opposite ends of the surrounding side. The body and the rotatable loop can rotate around a first axis and with respect to each other. The ear hook is pivotally mounted on one side of the rotatable loop near where the rotatable loop is connected with the body, and the ear hook can rotate around a second axis, which is different from the first axis. | 04-16-2009 |
Patent application number | Description | Published |
20110285950 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate includes a substrate, first scan lines, second scan lines, data lines, and pixels. The first and the second scan lines are alternately arranged along a first direction. The data lines are arranged in parallel along a second direction. The pixels are arranged to form first pixel rows and second pixel rows alternately arranged in the first direction. The first pixel row includes first and second pixels electrically connected to the first scan lines, the second scan lines, and the data line, respectively. The second pixel row includes third and fourth pixels electrically connected to the first scan lines, the second scan lines, and the data line, respectively. The pixels between two adjacent data lines are arranged in two columns. Among the pixels in the same column, the pixels in odd rows and in even rows are electrically connected to different data lines, respectively. | 11-24-2011 |
20130100006 | DISPLAY PANEL AND GATE DRIVING CIRCUIT THEREOF - A display panel and its gate driving circuit are provided. The gate driving circuit includes a plurality of shift registers. Each of the shift registers includes a first scan signal generator for generating a first scan signal, a second scan signal generator for generating a second scan signal, a first control unit for generating a first control signal, and a second control unit for generating a second control signal. Here, the first control signal and the second control signal are shared by the first scan signal generator and the second scan signal generator. Based on the above, the abatement of signal intensity of the first scan signal and the second scan signal caused by circuit sharing can be precluded, and a chip area occupied by each of the shift registers can be reduced. | 04-25-2013 |
20130293821 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate includes a substrate, first scan lines, second scan lines, data lines, and pixels. The first and the second scan lines are alternately arranged along a first direction. The data lines are arranged in parallel along a second direction. The pixels are arranged to form first pixel rows and second pixel rows alternately arranged in the first direction. The first pixel row includes first and second pixels electrically connected to the first scan lines, the second scan lines, and the data line, respectively. The second pixel row includes third and fourth pixels electrically connected to the first scan lines, the second scan lines, and the data line, respectively. The pixels between two adjacent data lines are arranged in two columns. Among the pixels in the same column, the pixels in odd rows and in even rows are electrically connected to different data lines, respectively. | 11-07-2013 |
20140063398 | DISPLAY PANEL AND REPAIRING METHOD THEREOF - A display panel is provided. A substrate includes a non-display area and a display area including a center area, a first area, and a second area. First data lines are disposed in the first area and electrically connected to the first source driving circuit. Second data lines are disposed in the second area and electrically connected to the second source driving circuit. At least one first repairing line is electrically connected to the first source driving circuit, passes through the center area of the display area and overlaps with the first data lines, wherein the first repairing line is electrically insulated from the first data lines. At least one second repairing line is electrically connected to the second source driving circuit, passes through the center area of the display area and overlaps with the second data lines, wherein the second repairing line is electrically insulated from the second data lines. | 03-06-2014 |
20140078127 | DISPLAY APPARATUS AND METHOD FOR GENERATING GATE SIGNAL THEREOF - A display apparatus and a method for generating gate signal thereof are provided. The display apparatus includes a timing controller and a display panel. The timing controller is used for providing a plurality of timing signals. The display panel includes a pixel array and a gate drive circuit. The pixel array has a plurality of pixels. The gate drive circuit is electrically connected to the timing controller and the pixel array and including a plurality of shift register circuits. The shift register circuit includes a first shift register and a second shift register. The first shift register is configured for generating a corresponding primary gate signal. The second shift register is configured for generating a corresponding secondary gate signal. The timing controller adjusts overlapping relations of the timing signals according to a frame rate of the display apparatus. | 03-20-2014 |