| Patent application number | Description | Published |
|---|
| 20080292001 | APPARATUS AND METHOD FOR CALCULATING SUM OF ABSOLUTE DIFFERENCES FOR MOTION ESTIMATION OF VARIABLE BLOCK - Provided are an apparatus and method for calculating a Sum of Absolute Differences (SAD) for motion estimation of a variable block capable of parallelly calculating SAD values with respect to a plurality of current frame macroblocks at a time. The apparatus includes a PE array unit including at least one Processing Element (PE) that is aligned in the form of a matrix, and parallelly calculating a SAD value of at least one pixel provided in a plurality of serial current frame macroblocks, a local memory including current frame macroblock data, reference frame macroblock data, and reference frame search area data, and transmitting the data to each PE that is provided in the PE array unit, and a controller for making a command for the data that are provided in the local memory to be transmitted corresponding to at least one pixel, on which each PE provided in the PE array unit performs calculation. | 11-27-2008 |
| 20080294875 | PARALLEL PROCESSOR FOR EFFICIENT PROCESSING OF MOBILE MULTIMEDIA - Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions. | 11-27-2008 |
| 20090144523 | MULTIPLE-SIMD PROCESSOR FOR PROCESSING MULTIMEDIA DATA AND ARITHMETIC METHOD USING THE SAME - A multiple-single instruction multiple data (SIMD) processor and an arithmetic method using the same are disclosed. When various arithmetic operations should be individually carried out by SIMD arithmetic units, control right is sub-divided to perform the arithmetic operations, such that the time of the arithmetic operations can be shortened and the efficiency thereof can be raised. When sub-divided control is not required, the control right is withdrawn and the arithmetic operations are carried out using a minimum number of program memories and a minimum number of SIMD arithmetic units, such that memory and power consumption thereof can be reduced. | 06-04-2009 |
| 20090150471 | RECONFIGURABLE ARITHMETIC UNIT AND HIGH-EFFICIENCY PROCESSOR HAVING THE SAME - Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for generating a plurality of partial products using the encoded multiplier and a multiplicand, a Wallace tree circuit for compressing the partial products into a first partial product and a second partial product, a first Multiplexer (MUX) for selecting and outputting one of the first partial product and a first addition input according to a selection signal, a second MUX for selecting and outputting one of the second partial product and a second addition input according to the selection signal, and a Carry Propagation Adder (CPA) for adding an output of the first MUX and an output of the second MUX to output an operation result. The arithmetic unit can operate as an adder or a multiplier according to an instruction, and thus can increase the degree of use of entire hardware. | 06-11-2009 |
| 20090282223 | DATA PROCESSING CIRCUIT - Provided is a data processing circuit. A control unit outputs an operation control signal and a memory control signal. A plurality of program memories each outputs a command in response to the memory control signal. A plurality of arithmetic sections each selectively performs any one of the commands from the plurality of program memories in response to the operation control signal. Operation modes of the data processing circuit can be flexibly changed according to operation environments. | 11-12-2009 |
| 20100135396 | IMAGE PROCESSING DEVICE - Provided is an image processing device. The image processing device includes: a plurality of operation units; and a controller unit storing an occurred bit amount to calculate a rate-distortion cost value and transmitting the occurred bit amount to each of the plurality of operation units, wherein at least one of the plurality of operation units calculates each distortion value with respect to a plurality of encoding modes and calculates each rate-distortion cost value with respect to the plurality of encoding modes using the calculated each distortion value and occurred bit amount. | 06-03-2010 |
| 20100162016 | LOW POWER CONSUMPTION PROCESSOR - Provided is a low power consumption processor. The processor includes: a plurality of blocks; a memory storing instructions that control each of the plurality of blocks; and a multi power controller generates a signal that activates at least one of the plurality of blocks according to an address storing the instruction, and provides a normal power voltage or a reduction power voltage in response to the activation signal. | 06-24-2010 |
| 20110022647 | APPARATUS FOR CALCULATING ABSOLUTE DIFFERENCE - Provided is an apparatus for calculating an absolute difference capable of efficiently performing an absolute difference using an adder. The apparatus for calculating an absolute difference includes a comparator comparing values of two integers, first and second selectors each selecting and outputting one of the two integers according to the comparison results of the comparator, an inverter complementing the result value selected by the second selector; and an adder adding up the result value selected by the first selector, the value complemented by the inverter, and 1. | 01-27-2011 |
| 20110022767 | DMA CONTROLLER WITH INTERRUPT CONTROL PROCESSOR - Provided is a direct memory access (DMA) controller having an interrupt control processor that can process DMA transmission-related interrupts according to a control program modifiable by a user. The DMA controller includes the interrupt control processor that can process a DMA transmission-related interrupt and a DMA request interrupt transmitted from peripheral devices and control the DMA channel through the control program that can be modified by the user, so that DMA channel control and relevant interrupt processing loads caused by a plurality of DMA data transmissions are reduced, and the flexibility of DMA channel control and interrupt processing in control of the DMA controller is provided to the user. | 01-27-2011 |
| 20110135191 | APPARATUS AND METHOD FOR RECOGNIZING IMAGE BASED ON POSITION INFORMATION - According to the present invention, the amount of computation required for image recognition processing can be reduced by extracting only image recognition learning information for an object that may appear in a region having the geographical property of a current position and comparing the image recognition learning information with ambient-image information. | 06-09-2011 |
| 20110142345 | APPARATUS AND METHOD FOR RECOGNIZING IMAGE - Provided are an apparatus and method for recognizing an image. In the apparatus and method for recognizing an image, various features can be extracted by a Haar-like filter using 1 | 06-16-2011 |
| 20110144859 | APPARATUS AND METHOD FOR PREVENTING COLLISION OF VEHICLE - The present invention provides an apparatus and method for predicting a moving direction of another vehicle running on a carriageway adjacent to a user's vehicle using periodically acquired image information around the user's vehicle, and performing a control process of preventing collision of the user's vehicle when a moving direction of the user's vehicle crosses the moving direction of the other vehicle. | 06-16-2011 |
| 20110145549 | PIPELINED DECODING APPARATUS AND METHOD BASED ON PARALLEL PROCESSING - An apparatus and method for decoding moving images based on parallel processing are provided. The apparatus for decoding images based on parallel processing can improve operational performance by pipelining massive-data transmission between processors while performing context-adaptive variable length decoding (CAVLD), inverse quantization (IQ), inverse transformation (IT), motion compensation (MC), intra prediction (IP) and deblocking filter (DF) operations in parallel in units of pluralities of macroblocks (MBs). | 06-16-2011 |
| 20110153878 | MEMORY SYSTEM AND INTEGRATED MANAGEMENT METHOD FOR PLURALITY OF DMA CHANNELS - Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller. | 06-23-2011 |
