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Chun-Chien
Chun-Chien Chen, Taipei County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090205852 | CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - A manufacturing method of a circuit board is provided. A metal core is provided. A conductive layer is formed on each of some carriers. The carriers and dielectric layers are laminated at both sides of the metal core to form a stacked structure. Each of the dielectric layers is located between the corresponding carrier and the metal core, and a portion of the conductive layer is embedded in the corresponding dielectric layer. Then, the carriers are removed. A blind via and/or a through via are/is formed in the stacked structure to connect the corresponding conductive layer and the metal core and/or connect the conductive layers at both sides of the metal core, wherein the through via penetrates the metal core. The conductive layer on a surface of the dielectric layer is removed. | 08-20-2009 |
| 20100044082 | WIRING BOARD - A wiring board including two wiring layers and a flexible core layer is provided. The flexible core layer is disposed between the wiring layers, and the flexible core layer is an insulator. A flexure of the wiring board is between 0 degree and 170 degrees. | 02-25-2010 |
| 20100065319 | WIRING BOARD AND PROCESS FOR FABRICATING THE SAME - A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed. | 03-18-2010 |
Chun-Chien Chen, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20080280032 | PROCESS OF EMBEDDED CIRCUIT STRUCTURE - A process of an embedded circuit structure is provided. A complex metal layer, a prepreg, a supporting board, another prepreg and another complex metal layer are laminated together, wherein each of the complex metal layers has an inner metal layer and an outer metal layer stacked on the inner metal layer, the roughness of the outer surfaces of the inner metal layers is less than the roughness of the second outer surfaces of the outer metal layers, and the outer surfaces of the outer metal layers after laminating are exposed outwards. Each of two patterned photoresist layers is respectively formed on the outer surfaces of the outer metal layers. A metal material is created on portions of the outer surfaces of the outer metal layers not covered by the patterned photoresist layers to form two patterned circuit layers. The patterned photoresist layers are then removed to form a laminating structure. | 11-13-2008 |
Chun-Chien Chen, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080196934 | CIRCUIT BOARD PROCESS - A circuit board process is provided. First, multiple carriers is provided, and a first conductive layer having multiple concave structures is formed on each carrier. A dielectric layer is then provided, and the carriers with the first conductive layers are laminated on a first and a second surface of the dielectric layer respectively, wherein portions of the first conductive layers are embedded in the first and second surfaces. Next, the carriers are removed. Thereafter, the first conductive layer corresponding to at least one concave is removed to expose a portion of the dielectric layer. Next, the exposed dielectric layer is removed to form an opening. A second conductive layer is then formed on the inner wall of the opening, wherein the second conductive layer is electrically connected to the first conductive layers on both sides of the dielectric layer. | 08-21-2008 |
Chun-Chien Tsai, Yongkang City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100289057 | INTEGRATED CIRCUITS USING GUARD RINGS FOR ESD, SYSTEMS, AND METHODS FOR FORMING THE INTEGRATED CIRCUITS - An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD). | 11-18-2010 |