Patent application number | Description | Published |
20110249635 | Wireless Apparatuses, Wireless Systems, and Methods for Managing Multiple Component Carriers - A wireless communications device with a wireless module and a controller module is provided. The wireless module performs wireless transceiving to and from a radio access network. The controller module receives a preamble assignment message comprising a component carrier indicator from the radio access network via the wireless module, and transmits, on a component carrier corresponding to the component carrier indicator, a Random Access Preamble (RAP) message to the radio access network via the wireless module. Also, the controller module receives a Random Access Response (RAR) message corresponding to the RAP message from the radio access network via the wireless module, and determines whether to activate the component carrier in response to one of the preamble assignment message, the RAP message, and the RAR message. | 10-13-2011 |
20120100851 | Apparatuses, Systems, and Methods for Inbound Handover Enhancement - A wireless communications device with a wireless module and a controller module is provided. The wireless module performs wireless transmission and reception to and from a service network comprising at least two first home base stations having the same physical cell identity (PCI) or physical scrambling code (PSC), a plurality of second home base stations neighboring the first home base stations, and a macro base station. The controller module receives a message from the macro base station via the wireless module, requests the wireless module to detect a plurality of PCIs or PSCs respectively corresponding to the first home base stations and the second home base stations in response to the message, and transmits to the macro base station via the wireless module the detected PCIs or PSCs, prior to being handed over to the one of the first home base stations from the macro base station. | 04-26-2012 |
Patent application number | Description | Published |
20090135909 | MOTION COMPENSATION METHOD AND INTEGRATED CIRCUIT UTILIZING THE SAME - An integrated circuit capable of motion compensation and a method thereof is disclosed. The integrated circuit comprises a partition unit and a motion compensation unit. The partition unit receives a video block having a predetermined block dimension, and partitions the video block into sub-blocks with a sub-block dimension less than the predetermined block dimension when the video block is on a frame boundary of a video frame. The motion compensation unit, coupled to the partition unit, performs motion compensation on the sub-blocks. | 05-28-2009 |
20090237406 | CHARACTER RENDERING SYSTEM - To facilitate a low-power/power-aware, high-speed, and high-quality/quality-adaptive character rendering process, a character rendering system including a memory, a cache unit, a Bezier curve parallel decomposition module, a transfer controller, a parallel anti-aliasing module, a buffer, and a scan conversion unit is disclosed. The cache unit stores a plurality of Bezier curve key points corresponding to frequently used characters. The Bezier curve parallel decomposition module performs parallel decomposing processes on the Bezier curves of the Bezier curve key points corresponding to a character for generating a plurality of segments. The parallel anti-aliasing module performs parallel anti-aliasing processes on data of the segments transferred by the transfer controller for generating edge pixel data. The edge pixel data are transferred to the scan conversion unit via the memory or the buffer. The scan conversion unit performs a scan conversion process on the edge pixel data for generating image data of the character. | 09-24-2009 |
20100046629 | VIDEO DECODING SYSTEM AND METHOD THEREOF - A video decoding method includes: (a) computing location relations between an original frame and a resized frame to which the frame is to be scaled; (b) mapping a location of a data unit of the original frame to a location of a corresponding data unit of the resized frame according to the location relations; and (c) scaling the data unit of the original frame to the corresponding data unit of the resized frame. | 02-25-2010 |
20120089360 | Algorithm Integrating System and Integrating Method Thereof - The present invention discloses an algorithm integrating system and an integrating method thereof. The algorithm integrating system comprises a receiving module, an analyzing module, and a processing module. The receiving module receives at least one test algorithm. The analyzing module is connected to the receiving module and analyzes the at least one test algorithm to obtain at least one basic element from the at least one test algorithm. The processing module is connected to the analyzing module and screen out the at least one non-duplicate basic element based on the at least one basic element. Then, the processing module integrates the at least one non-duplicate basic element and generates a testing module. | 04-12-2012 |
20140292790 | METHOD AND APPARATUS FOR ARRANGING PIXELS OF PICTURE IN STORAGE UNITS EACH HAVING STORAGE SIZE NOT DIVISIBLE BY PIXEL SIZE - An exemplary data arrangement method for a picture includes at least the following steps: obtaining pixel data of a plurality of first N-bit pixels of the picture; and storing the obtained pixel data of the first N-bit pixels in a plurality of M-bit storage units of a first buffer based on a raster-scan order of the picture, wherein M and N are positive integers, and M is not divisible by N. Besides, at least one of the M-bit storage units is filled with part of the obtained pixel data of the first N-bit pixels, and the first N-bit pixels include at least one pixel divided into a first part stored in one of the M-bit storage units in the first buffer and a second part stored in another of the M-bit storage units in the first buffer. | 10-02-2014 |
20140294090 | METHOD AND APPARATUS FOR ARRANGING PIXELS OF PICTURE IN STORAGE UNITS EACH HAVING STORAGE SIZE NOT DIVISIBLE BY PIXEL SIZE - A data arrangement method includes following steps: obtaining pixel data of a plurality of first N-bit pixels of a picture; and storing the obtained pixel data of the first N-bit pixels in a plurality of M-bit storage units of a first buffer according to a block-based scan order of the picture. The picture includes a plurality of data blocks, and the block-based scan order includes a raster-scan order for the data blocks. At least one of the M-bit storage units is filled with part of the obtained pixel data of the first N-bit pixels, M and N are positive integers, M is not divisible by N, and the first N-bit pixels include at least one pixel divided into a first part stored in one of the M-bit storage units in the first buffer and a second part stored in another of the M-bit storage units in the first buffer. | 10-02-2014 |
20150326875 | VIDEO PROCESSING METHOD FOR DETERMINING POSITION OF REFERENCE BLOCK OF RESIZED REFERENCE FRAME AND RELATED VIDEO PROCESSING APPARATUS - A video processing method includes: receiving a motion vector of a prediction block in a current frame; performing a first motion vector scaling operation upon the motion vector to generate a first scaled motion vector; after the first scaled motion vector is generated, utilizing a motion vector clamping circuit for performing a first motion vector clamping operation upon the first scaled motion vector to generate a first clamped motion vector; and determining a position of a reference block of a reference frame according to at least the first clamped motion vector. | 11-12-2015 |
20160029022 | VIDEO PROCESSING APPARATUS WITH ADAPTIVE CODING UNIT SPLITTING/MERGING AND RELATED VIDEO PROCESSING METHOD - A video processing apparatus includes a first processing circuit, a second processing circuit, and a control circuit. The first processing circuit performs a first processing operation. The second processing circuit performs a second processing operation different from the first processing operation. The control circuit generates at least one output coding unit to the second processing circuit according to an input coding unit generated from the first processing circuit, wherein the control circuit checks a size of the input coding unit to selectively split the input coding unit into a plurality of output coding units. | 01-28-2016 |
20160080771 | MOTION COMPENSATION APPARATUS HAVING AT LEAST ONE PROCESSING CIRCUIT SHARED BY NORMAL MODE AND RESIZED REFERENCE FRAME MODE AND RELATED MOTION COMPENSATION METHOD - A motion compensation apparatus includes an interpolation filter device, a pixel fetching circuit, and a pixel dispatching circuit. The interpolation filter device generates interpolated pixels by performing interpolation according to reference pixels. The pixel fetching circuit fetches the reference pixels from a reference frame. The pixel dispatching circuit dispatches pixels to the interpolation filter device, wherein the pixels comprise the reference pixels. At least one of the interpolation filter device, the pixel fetching circuit and the pixel dispatching circuit is shared by a normal mode and a resized reference frame (RRF) mode of motion compensation. | 03-17-2016 |
Patent application number | Description | Published |
20110002087 | Stacked capacitor with positive multi-pin structure - A stacked capacitor with positive multi-pin structure includes a plurality of capacitor units, a substrate unit and a package unit. Each capacitor unit has a positive electrode that has a positive pin extended outwards therefrom. The positive pins of the capacitor units are divided into a plurality of positive pin units that are separated from each other, and the positive pins of each positive pin unit are electrically stacked onto each other. Each capacitor unit has a negative electrode, and the negative electrodes of the capacitor units are electrically stacked onto each other. The substrate unit has a positive guiding substrate electrically connected to the positive pins of the capacitor units and a negative guiding substrate electrically connected to the negative electrodes of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit. | 01-06-2011 |
20110007451 | STACKED SOLID ELECTROLYTIC CAPACITOR WITH MULTI-PIN STRUCTURE - A stacked solid electrolytic capacitor with positive multi-pin structure includes a plurality of capacitor units, a substrate unit and a package unit. The positive electrode of each capacitor unit has a positive pin extended outwards therefrom. The positive pins are divided into a plurality of positive pin units that are separated from each other and electrically stacked onto each other. The negative electrode of each capacitor unit has a negative pin extended outwards therefrom. The negative pins are divided into a plurality of negative pin units. The negative pin units are separated from each other and the negative pins of each negative pin unit are electrically stacked onto each other. The substrate unit has a positive guiding substrate electrically connected to the positive pins and a negative guiding substrate electrically connected to the negative pins. The package unit covers the capacitor units and one part of the substrate unit. | 01-13-2011 |
20110122544 | STACKED SOLID ELECTROLYTIC CAPACITOR AND A METHOD FOR MANUFACTURING THE SAME - A stacked solid electrolytic capacitor and a method for manufacturing the same are disclosed. The stacked solid electrolytic capacitor includes two capacitor sets, a positive electrode conducting device, a negative electrode conducting device, and a package unit. Each capacitor set includes at least one capacitor unit. The front side of the positive electrode portion of the capacitor set extends to form a positive electrode pin. The positive electrode conducting device has at least one first positive electrode conducting lead frame and at least one second positive electrode conducting lead frame. The first positive electrode conducting lead frame is electrically connected with the second positive electrode conducting lead frame. The negative electrode conducting device has at least one negative electrode conducting lead frame, and is electrically connected with the negative electrode of the two capacitor sets by using metal conductive material. | 05-26-2011 |