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Chun-Chia
Chun-Chia Chen, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090135909 | MOTION COMPENSATION METHOD AND INTEGRATED CIRCUIT UTILIZING THE SAME - An integrated circuit capable of motion compensation and a method thereof is disclosed. The integrated circuit comprises a partition unit and a motion compensation unit. The partition unit receives a video block having a predetermined block dimension, and partitions the video block into sub-blocks with a sub-block dimension less than the predetermined block dimension when the video block is on a frame boundary of a video frame. The motion compensation unit, coupled to the partition unit, performs motion compensation on the sub-blocks. | 05-28-2009 |
| 20090237406 | CHARACTER RENDERING SYSTEM - To facilitate a low-power/power-aware, high-speed, and high-quality/quality-adaptive character rendering process, a character rendering system including a memory, a cache unit, a Bezier curve parallel decomposition module, a transfer controller, a parallel anti-aliasing module, a buffer, and a scan conversion unit is disclosed. The cache unit stores a plurality of Bezier curve key points corresponding to frequently used characters. The Bezier curve parallel decomposition module performs parallel decomposing processes on the Bezier curves of the Bezier curve key points corresponding to a character for generating a plurality of segments. The parallel anti-aliasing module performs parallel anti-aliasing processes on data of the segments transferred by the transfer controller for generating edge pixel data. The edge pixel data are transferred to the scan conversion unit via the memory or the buffer. The scan conversion unit performs a scan conversion process on the edge pixel data for generating image data of the character. | 09-24-2009 |
| 20100046629 | VIDEO DECODING SYSTEM AND METHOD THEREOF - A video decoding method includes: (a) computing location relations between an original frame and a resized frame to which the frame is to be scaled; (b) mapping a location of a data unit of the original frame to a location of a corresponding data unit of the resized frame according to the location relations; and (c) scaling the data unit of the original frame to the corresponding data unit of the resized frame. | 02-25-2010 |
Chun-Chia Chen, Taipei Hsien TW
| Patent application number | Description | Published |
|---|---|---|
| 20110170535 | Method of Handling Uplink Synchronization and Related Communication Device - A method of handling uplink synchronization for a mobile device capable of receiving and transmitting on a plurality of component carriers in a wireless communication system is disclosed. The method comprises performing a first random access procedure on a first component carrier of the plurality of component carriers to establish uplink synchronization on the first component carrier, and performing a second random access procedure on at least a component carrier of the plurality of component carriers to establish uplink synchronization on the at least a component carrier. | 07-14-2011 |
Chun-Chia Chen, Zhutang Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20110249635 | Wireless Apparatuses, Wireless Systems, and Methods for Managing Multiple Component Carriers - A wireless communications device with a wireless module and a controller module is provided. The wireless module performs wireless transceiving to and from a radio access network. The controller module receives a preamble assignment message comprising a component carrier indicator from the radio access network via the wireless module, and transmits, on a component carrier corresponding to the component carrier indicator, a Random Access Preamble (RAP) message to the radio access network via the wireless module. Also, the controller module receives a Random Access Response (RAR) message corresponding to the RAP message from the radio access network via the wireless module, and determines whether to activate the component carrier in response to one of the preamble assignment message, the RAP message, and the RAR message. | 10-13-2011 |
Chun-Chia Chen, Taichung County TW
| Patent application number | Description | Published |
|---|---|---|
| 20120012938 | METHOD OF MANUFACTURING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE - A method of manufacturing a CMOS device includes providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure, each of the gate structures comprising a sacrificial layer and a hard mask layer; forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure; performing an etching process to form first recesses in the substrate; performing a SEG process to form epitaxial silicon layers in each first recess; forming a patterned second protecting layer covering the second region; and performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure. | 01-19-2012 |
Chun-Chia Huang, Taipei County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100202815 | INTERLOCKED ROLL TYPE APPARATUS - An interlocked roll type apparatus comprises: a first spool, two first flanges, a second spool, and two second flanges. The first flange has a first surface, a second surface, and a first periphery surface. The first surface has a first round protruding part. The first periphery surface has at least a first arc part, and the first arc part has a first arc protruding part protruding from the first surface. The second flange has a third surface, a fourth surface, and a second periphery surface. The second periphery surface has at least a second arc part having a second arc protruding part protruding from the third surface. The second arc part and the second arc protruding part are fastened with the first round protruding part of the first flange. The fourth surface has a second arc trench part for fastened with the first arc protruding part of the first flange. | 08-12-2010 |
Chun-Chia Huang, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100084811 | PRINTING MEDIA LOADING APPARATUS - A printing media loading apparatus includes a roller that has a narrow slit thereon and is used for loading a printing media. There are two nicks respectively on the two sides of the roller, and the narrow slit extends to the two nicks. The printing media loading apparatus further includes at least a detachable fixing unit, installed in a nick on one of the two sides of the roller for fixing the diameter of the roller. | 04-08-2010 |
Chun-Chia Huang, Xinying City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110002087 | Stacked capacitor with positive multi-pin structure - A stacked capacitor with positive multi-pin structure includes a plurality of capacitor units, a substrate unit and a package unit. Each capacitor unit has a positive electrode that has a positive pin extended outwards therefrom. The positive pins of the capacitor units are divided into a plurality of positive pin units that are separated from each other, and the positive pins of each positive pin unit are electrically stacked onto each other. Each capacitor unit has a negative electrode, and the negative electrodes of the capacitor units are electrically stacked onto each other. The substrate unit has a positive guiding substrate electrically connected to the positive pins of the capacitor units and a negative guiding substrate electrically connected to the negative electrodes of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit. | 01-06-2011 |
| 20110007451 | STACKED SOLID ELECTROLYTIC CAPACITOR WITH MULTI-PIN STRUCTURE - A stacked solid electrolytic capacitor with positive multi-pin structure includes a plurality of capacitor units, a substrate unit and a package unit. The positive electrode of each capacitor unit has a positive pin extended outwards therefrom. The positive pins are divided into a plurality of positive pin units that are separated from each other and electrically stacked onto each other. The negative electrode of each capacitor unit has a negative pin extended outwards therefrom. The negative pins are divided into a plurality of negative pin units. The negative pin units are separated from each other and the negative pins of each negative pin unit are electrically stacked onto each other. The substrate unit has a positive guiding substrate electrically connected to the positive pins and a negative guiding substrate electrically connected to the negative pins. The package unit covers the capacitor units and one part of the substrate unit. | 01-13-2011 |
| 20110122544 | STACKED SOLID ELECTROLYTIC CAPACITOR AND A METHOD FOR MANUFACTURING THE SAME - A stacked solid electrolytic capacitor and a method for manufacturing the same are disclosed. The stacked solid electrolytic capacitor includes two capacitor sets, a positive electrode conducting device, a negative electrode conducting device, and a package unit. Each capacitor set includes at least one capacitor unit. The front side of the positive electrode portion of the capacitor set extends to form a positive electrode pin. The positive electrode conducting device has at least one first positive electrode conducting lead frame and at least one second positive electrode conducting lead frame. The first positive electrode conducting lead frame is electrically connected with the second positive electrode conducting lead frame. The negative electrode conducting device has at least one negative electrode conducting lead frame, and is electrically connected with the negative electrode of the two capacitor sets by using metal conductive material. | 05-26-2011 |