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| 20080201672 | CASCADED PASS-GATE TEST CIRCUIT WITH INTERPOSED SPLIT-OUTPUT DRIVE DEVICES - A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate. | 08-21-2008 |
| 20080278992 | INDEPENDENT-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USING THE CELL - Techniques are provided for employing independent gate control in asymmetrical memory cells. A memory circuit, such as an SRAM circuit, can include a number of bit line structures, a number of word line structures that intersect the bit line structures to form a number of cell locations, and a number of asymmetrical memory cells located at the cell locations. Each of the asymmetrical cells can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each of the cells can include a number of field effect transistors (FETS), and at least one of the FETS can be configured with separately biased front and back gates. One gate can be biased separately from the other gate in a predetermined manner to enhance read stability of the asymmetrical cell. | 11-13-2008 |
| 20090067223 | COMPUTER-READABLE MEDIUM ENCODING A BACK-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USING THE CELL - Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters. | 03-12-2009 |
| 20090302894 | DUAL GATE TRANSISTOR KEEPER DYNAMIC LOGIC - A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation. | 12-10-2009 |
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| 20090018787 | APPARATUS AND METHOD FOR DETERMINING THE SLEW RATE OF A SIGNAL PRODUCED BY AN INTEGRATED CIRCUIT - Determining a slew rate of a signal from an integrated circuit under test by comparing the signal with a first reference voltage, comparing the signal with a second reference voltage different from the first reference voltage, generating an output pulse having a pulse width indicative of a slew rate of the signal, and integrating the output pulse over time to generate an output voltage proportional to the pulse width; wherein the output voltage is indicative of the slew rate of the signal produced by the integrated circuit. | 01-15-2009 |
| 20090091346 | CIRCUITS AND METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CIRCUITS - A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level. | 04-09-2009 |
| 20090185409 | ENHANCED STATIC RANDOM ACCESS MEMORY STABILITY USING ASYMMETRIC ACCESS TRANSISTORS AND DESIGN STRUCTURE FOR SAME - A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the | 07-23-2009 |
| 20090189703 | CIRCUITS AND DESIGN STRUCTURES FOR MONITORING NBTI (NEGATIVE BIAS TEMPERATURE INSTABILITY) EFFECT AND/OR PBTI (POSITIVE BIAS TEMPERATURE INSTABILITY) EFFECT - A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals. Also included are an analogous NAND-gate based circuit, a circuit combining the NAND- and NOR-aspects, a circuit with a ring oscillator where the inverters may be coupled directly or through inverting paths, and circuits for measuring the bias temperature instability effect in pass gates. | 07-30-2009 |
| 20090190426 | CIRCUITS, METHODS AND DESIGN STRUCTURES FOR ADAPTIVE REPAIR OF SRAM ARRAYS - The circuit includes a static random access memory array having a plurality of cells, in turn having a plurality of devices; as well as a global sensor having at least one output, coupled to the static random access memory array, and configured to sense at least one of global readability and global write-ability. Also included is a decision-making circuit coupled to the at least one output of the global sensor. The decision-making circuit is configured to determine, from the at least one output of the global sensor, whether adaptation signals are required to correct global readability and/or write-ability. An adaptation signal generation block is also included and is coupled to the decision-making circuit and the array, and configured to supply the adaptation signals to the array, responsive to the decision-making circuit determining that the adaptation signals are required. At least the array and the global sensor, and preferably the decision-making circuit and the adaptation signal generation block as well, are implemented on a single integrated circuit chip. An associated method and design structure(s) are also provided. | 07-30-2009 |
| 20090302354 | High Density Stable Static Random Access Memory - A memory circuit includes a plurality of bit line structures, a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells is selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures, and each of the cells in turn includes a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor. The at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of the bit line structures, and the at least first p-type field effect transistor is formed with a relatively thin buried oxide layer | 12-10-2009 |
| 20090310430 | METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CIRCUITS - A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level. | 12-17-2009 |
| 20110173577 | Techniques for Pattern Process Tuning and Design Optimization for Maximizing Process-Sensitive Circuit Yields - Techniques for improving circuit design and production are provided. In one aspect, a method for virtual fabrication of a process-sensitive circuit is provided. The method comprises the following steps. Based on a physical layout diagram of the circuit, a virtual representation of the fabricated circuit is obtained that accounts for one or more variations that can occur during a circuit production process. A quality-based metric is used to project a production yield for the virtual representation of the fabricated circuit. The physical layout diagram and/or the production process are modified. The obtaining, using and modifying steps are repeated until a desired projected production yield is attained. | 07-14-2011 |
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| 20090302929 | Methods and Apparatus for Varying a Supply Voltage or Reference Voltage Using Independent Control of Diode Voltage in Asymmetrical Double-Gate Devices - Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit. | 12-10-2009 |
| 20090303778 | Methods and Apparatus for Varying a Supply Voltage or Reference Voltage Using Independent Control of Diode Voltage in Asymmetrical Double-Gate Devices - Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit. | 12-10-2009 |
| 20100026346 | HIGH-DENSITY LOGIC TECHNIQUES WITH REDUCED-STACK MULTI-GATE FIELD EFFECT TRANSISTORS - Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced. | 02-04-2010 |
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| 20080299418 | Fuel Cell Stack with Improved End Cell Performance - A fuel cell stack that includes a gas diffusion media for the end cells in the stack that has less of an intrusion into the flow field channels of the end cells that the other cells, so as to increase the flow rate through the flow channels in the end cells relative to the flow rate through the flow channels in the other cells. A different diffusion media can be used in the end cells than the nominal cells, where the end cell diffusion media has less of a channel intrusion as a result of diffusion media characteristics. Also, the same diffusion media could be used in the end cells as the nominal cells, but the end cell diffusion media layers could be thinner than the nominal cell diffusion media layers. Further, a higher amount of pre-compression can be used for the diffusion media in the end cells. | 12-04-2008 |
| 20110076583 | FUEL CELL WITH ANODE AND CATHODE PLATE TEMPERATURE DIFFERENCE - A method of operating a fuel cell is described. The method includes controlling the temperature of the anode plate and the temperature of the cathode plate to obtain a temperature difference of at least about 2° C. between the anode plate and the cathode plate. A fuel cell is also described. | 03-31-2011 |
| 20110143262 | GAS DIFFUSION MEDIA MADE FROM ELECTRICALLY CONDUCTIVE COATINGS ON NON-CONDUCTIVE FIBERS - A fuel cell includes a first electrically conductive plate and a first gas diffusion layer. The first gas diffusion layer is disposed over the first electrically conductive plate. Characteristically, the first gas diffusion layer comprises a first fibrous sheet having fibers coated with an electrically conductive layer. A first catalyst layer is disposed over the first gas diffusion layer and an ion conducting membrane is disposed over the first catalyst layer. The fuel cell also includes a second catalyst layer disposed over the ion conducting membrane with a second gas diffusion layer disposed over the second catalyst layer. A second electrically conductive plate is disposed over the second gas diffusion layer. Methods for forming the gas diffusion layers and the fuel cell are also provided. | 06-16-2011 |
| 20110192282 | OPTIMIZED GAS DIFFUSION MEDIA TO IMPROVE FUEL CELL PERFORMANCE - A gas diffusion media is described. The gas diffusion media comprises a conductive porous substrate; and a microporous layer; wherein a cathode effective transport length is in a range of about 700 to about 1900 μm; wherein an overall thermal resistance is in a range of about 1.8 to about 3.8 cm | 08-11-2011 |
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| 20120001293 | SEMICONDUCTOR ON GLASS SUBSTRATE WITH STIFFENING LAYER AND PROCESS OF MAKING THE SAME - A semiconductor-on-glass substrate having a relatively stiff (e.g. relatively high Young's modulus of 125 or higher) stiffening layer or layers placed between the silicon film and the glass in order to eliminate the canyons and pin holes that otherwise form in the surface of the transferred silicon film during the ion implantation thin film transfer process. The new stiffening layer may be formed of a material, such as silicon nitride, that also serves as an efficient barrier against penetration of sodium and other harmful impurities from the glass substrate into the silicon film. | 01-05-2012 |
| 20120003813 | OXYGEN PLASMA CONVERSION PROCESS FOR PREPARING A SURFACE FOR BONDING - A process for preparing a surface of a material that is not bondable to make it bondable to the surface of another material. A non-bondable surface of a semiconductor wafer is treated with oxygen plasma to oxidize the surface of the wafer and make the surface smoother, hydrophilic and bondable to the surface of another substrate, such as a glass substrate. The semiconductor wafer may have a barrier layer thereon formed of a material, such as SixNy or SiNxOy that is not bondable to another substrate, such as a glass substrate. In which case, the oxygen plasma treatment converts the surface of the barrier layer to oxide, such as SiO2, smoothing the surface and making the surface hydrophilic and bondable to the surface of another substrate, such as a glass substrate. The converted oxide layer may be stripped from the barrier layer or semiconductor wafer with an acid, in order to remove contamination on the surface of the barrier layer or semiconductor wafer, the stripped surface may undergo a second oxygen plasma treatment to further smooth the surface, and make the surface hydrophilic and bondable to the surface of another substrate | 01-05-2012 |
