Chuang, Hsinchu City

Che-Hao Chuang, Hsinchu City TW

Patent application number	Description	Published
20080232013	High-Voltage Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Interface - A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.	09-25-2008
20090032837	ASYMMETRIC BIDIRECTIONAL SILICON-CONTROLLED RECTIFIER - The present invention discloses an asymmetric bidirectional silicon-controlled rectifier, which comprises: a second conduction type substrate; a first conduction type undoped epitaxial layer formed on the substrate; a first well and a second well both formed inside the undoped epitaxial layer and separated by a portion of the undoped epitaxial layer; a first buried layer formed in a junction between the first well and the substrate; a second buried layer formed in a junction between the second well and the substrate; a first and a second semiconductor area with opposite conduction type both formed inside the first well; a third and a fourth semiconductor area with opposite conduction type both formed inside the second well, wherein the first and second semiconductor areas are connected to the anode of the silicon-controlled rectifier, and the third and fourth semiconductor areas are connected to the cathode of the silicon-controlled rectifier.	02-05-2009
20090032838	SYMMETRIC BIDIRECTIONAL SILICON-CONTROLLED RECTIFIER - The present invention discloses a symmetric bidirectional silicon-controlled rectifier, which comprises: a substrate; a buried layer formed on the substrate; a first well, a middle region and a second well, which are sequentially formed on the buried layer side-by-side; a first semiconductor area and a second semiconductor area both formed inside the first well; a third semiconductor area formed in a junction between the first well and the middle region, wherein a first gate is formed over a region between the second and third semiconductor areas; a fourth semiconductor area and a fifth semiconductor area both formed inside the second well; a sixth semiconductor area formed in a junction between the second well and the middle region, wherein a second gate is formed over a region between the fifth and sixth semiconductor areas.	02-05-2009
20090179679	SLEW-RATE CONTROL CIRCUITRY WITH OUTPUT BUFFER AND FEEDBACK - The present invention proposed a slew-rate control circuitry without the use of external components such as amplifiers. Therefore slew-rate control circuitry of the present invention not only provides an IC with build-in slew-rate control, but also reduces number of transistors used externally which will increase gate-oxide reliability of the IC. The slew-rate control circuitry of the present invention is primarily comprised by an output buffer and feedback circuitry, the output buffer mainly consisted four transistors and depends on output of the IC, these four transistors will interact with each other to control the slew-rate of IC output. Additional feedback circuitry and gate-tracking circuitry are also disclosed to enhance the performance of the slew-rate control circuitry.	07-16-2009
20120012973	LATERAL TRANSIENT VOLTAGE SUPPRESSOR WITH ULTRA LOW CAPACITANCE - A lateral transient voltage suppressor with ultra low capacitance is disclosed. The suppressor comprises a first type substrate and at least one diode cascade structure arranged in the first type substrate. The cascade structure further comprises at least one second type lightly doped well and at least one first type lightly doped well, wherein there are two heavily doped areas arranged in the second type lightly doped well and the first type lightly doped well. The cascade structure neighbors a second type well, wherein there are three heavily doped areas arranged in the second type well. The suppressor further comprises a plurality of deep isolation trenches arranged in the first type substrate and having a depth greater than depths of the second type lightly doped well, the second type well and the first type lightly doped well. Each doped well is isolated by trenches.	01-19-2012
20120012974	LATERAL TRANSIENT VOLTAGE SUPPRESSOR FOR LOW-VOLTAGE APPLICATIONS - A lateral transient voltage suppressor for low-voltage applications is disclosed. The suppressor comprises an N-type heavily doped substrate and at least two clamp diode structures horizontally arranged in the N-type heavily doped substrate. Each clamp diode structure further comprises a clamp well arranged in the N-type heavily doped substrate and having a first heavily doped area and a second heavily doped area. The first and second heavily doped areas respectively belong to opposite types. There is a plurality of deep isolation trenches arranged in the N-type heavily doped substrate and having a depth greater than depth of the clamp well. The deep isolation trenches can separate each clamp well. The present invention avoids the huge leakage current to be suitable for low-voltage application.	01-19-2012
20120014027	TRANSIENT VOLTAGE SUPPRESSOR FOR MULTIPLE PIN ASSIGNMENTS - A transient voltage suppressor (TVS) for multiple pin assignments is disclosed. The suppressor comprises at least two cascade-diode circuits in parallel to each other and an electrostatic-discharge clamp element in parallel to each cascade-diode circuit and connected with a low voltage. One cascade-diode circuit is connected with a high voltage, and the other cascade-diode circuits are respectively connected with I/O pins. Each cascade-diode circuit further comprises a first diode and a second diode cascaded to the first diode, wherein a node between the first diode and the second diode is connected with the high voltage or the one I/O pin. The design of the present invention can meet several bounding requirements. It is flexible different pin assignments of TVS parts.	01-19-2012
20120025350	VERTICAL TRANSIENT VOLTAGE SUPPRESSORS - A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region.	02-02-2012
20120068299	TRANSIENT VOLTAGE SUPPRESSORS - The present invention relates a transient voltage suppressor (TVS) for directional ESD protection. The TVS includes: a conductivity type substrate; a first type lightly doped region, having a first type heavily doped region arranged therein; a second type lightly doped region, having a second type heavily doped region and a third type heavily doped region arranged therein; a third type lightly doped region, having a fourth type heavily doped region arranged therein; a plurality of closed isolation trenches, arranged on the conductivity type substrate, wherein at least one of the plurality of closed isolation trenches is neighbored one of the type lightly doped regions; and a first pin. Accordingly, the TVS of present invention may adaptively provide effective ESD protection under positive and negative ESD stresses, improve the efficiency of ESD protection within the limited layout area.	03-22-2012

Patent applications by Che-Hao Chuang, Hsinchu City TW

Che Lun Chuang, Hsinchu City TW

Patent application number	Description	Published
20090161951	METHOD FOR CORRECTING RED-EYE - A method for correcting red-eye is described. Through facial features, at least one facial region is obtained in an image, a nose position in each facial region is obtained by using a nose feature, and at least one eye position is obtained based on a relative position relation between the nose and the eyes. After a color gamut of the image is converted, a red region is obtained from the eye position, and a plurality of edges is formed by using a luminance of the color gamut on the image with the converted color gamut according to the eye feature, so as to exclude the red region out of the plurality of edges, thereby improving accuracy of the red region on the eye position. Then, the red region is covered by an iris color, so as to correct the red-eye.	06-25-2009
20100208990	COMPENSATION METHOD FOR ALLEVIATING COLOR SHADING IN DIGITAL IMAGE - A compensation method for alleviating color shading in a digital image is adapted to correct a color shading phenomenon in a digital image that causes luminance differences between regions in the digital image. The compensation method includes capturing a uniform color block image; calculating horizontal compensation coefficients of a plurality of horizontal segments of the color block image; performing a linear interpolation process on the horizontal compensation coefficients to generate corresponding horizontal interpolation coefficients, and calculating determination horizontal correction coefficients corresponding to all the horizontal segments, respectively; calculating vertical compensation coefficients of a plurality of vertical segments; multiplying the determination horizontal correction coefficients by the vertical compensation coefficients, respectively, so as to obtain a color shading compensation coefficient of each segment, respectively; and multiplying an average luminance value of each segment by a corresponding color shading compensation coefficient, respectively, thus compensating for color shading in the color block image.	08-19-2010
20110158514	METHOD FOR REMOVING COLOR FRINGE IN DIGITAL IMAGE - A method for removing color fringe is presented. Separated luminance and chrominance (YCbCr) signals of a digital image are analyzed through specific color detection, luminance detection, and gradient color detection, so as to determine whether color fringe occurs to each pixel in the digital image, thereby correcting pixels with color fringe.	06-30-2011
20110158515	METHOD FOR REMOVING COLOR FRINGE IN DIGITAL IMAGE - A method for removing color fringe is presented. First, detection and correction of color fringe are performed on an original-size image and a small-size image respectively, so as to generate respective corrected images and corresponding color fringe maps. Then, the corrected small-size image and its corresponding color fringe map are enlarged to the same resolution as the original-size image. Finally, the two corrected images are blended according to the respective corresponding color fringe maps.	06-30-2011

Patent applications by Che Lun Chuang, Hsinchu City TW

Cheng Te Chuang, Hsinchu City TW

Patent application number	Description	Published
20110157421	Systems and Methods for Capturing Images of Objects - A method for generating an image object, performed by a mobile electronic device, comprises the following steps. The mobile electronic device comprises multiple shutter objects, and each shutter object corresponds to an orientation type. A signal generated by one of the shutter objects is detected. A orientation type is determined according to the shutter object generating the signal. The image object with the determined orientation type is stored.	06-30-2011

Chen-Jung Chuang, Hsinchu City TW

Patent application number	Description	Published
20100271294	Method for Reducing Resonance Energy of an LCD panel and Related LCD Device - A method for reducing resonance energy of an LCD panel includes providing a plurality of driving signal patterns, each defining a non-overlap area width of a synchronization signal and a scan-line charging frequency, and determining an order of the plurality of driving signal patterns to modulate driving signals of the LCD panel accordingly.	10-28-2010
20110001534	Voltage Generator Capable of Preventing Latch-up and Method Thereof - A voltage generator capable of preventing latch-up is disclosed. The voltage generator includes a positive charge pump unit, a negative charge pump unit, a second stage charge pump unit, and a control unit. The positive charge pump unit is utilized for generating a positive charge pump voltage according to a first enable signal. The negative charge pump is utilized for generating a negative charge pump voltage according to a second enable signal. The second stage charge pump unit is utilized for generating a gate-on voltage and a gate-off voltage according to a third enable signal and a fourth enable signal. The control unit is utilized for generating the first enable signal, the second enable signal, the third enable signal, and the fourth enable signal and make the second stage charge pump unit generate the gate-on voltage (or the gate-off voltage) in a successively-increasing (or decreasing) manner.	01-06-2011
20110012671	Charge Pump Circuit - A charge pump circuit includes an input end, a first reservoir capacitor, a second reservoir capacitor, a first output end, a second output end, and a charge pump unit. The input end is utilized for receiving an input voltage. The charge pump unit includes a first flying capacitor, a second capacitor, a plurality of switches, and a control unit. The control unit is utilized for controlling on/off state of the plurality of switches so that the first flying capacitor provides a positive charge pump voltage to the first output end or a negative charge pump voltage to the second output and the second flying capacitor provides a positive charge pump voltage to the first output end through charge and discharge process.	01-20-2011

Chia-Lin Chuang, Hsinchu City TW

Patent application number	Description	Published
20090051040	POWER LAYOUT OF INTEGRATED CIRCUITS AND DESIGNING METHOD THEREOF - The invention discloses a technique for designing the power layout of an integrated circuit. The power layout design forms a power mesh and a power ring with a plurality of metal trunks with uniform line width. In particular, the power ring includes a plurality of metal rings, which are formed by arranging denser layout of the metal trunks with uniform line width. The power ring serves as a function of receiving and providing a power source to the elements of the integrated circuit.	02-26-2009
20090132988	POWER MESH ARRANGEMENT METHOD UTILIZED IN AN INTEGRATED CIRCUIT HAVING MULTIPLE POWER DOMAINS - The invention discloses a power mesh arrangement method utilized in an integrated circuit having multiple power domains. The arrangement method includes: forming a first partial local power mesh according to a position of a first power domain; forming a second partial local power mesh according to a position of a second power domain; forming a global power mesh, utilized for providing powers needed by the first and the second power domains; coupling the first partial local power mesh to the global power mesh and the first power domain; and coupling the second partial local power mesh to the global power mesh and the second power domain.	05-21-2009
20090193271	POWER MESH MANAGEMENT METHOD - The invention discloses a power mesh managing method utilized in an integrated circuit. The integrated circuit includes a standard cell and a standard-cell power supplying mesh corresponding to a first direction. The power mesh managing method includes: defining a power supplying network including a first plurality of power meshes growing along the first direction and a second plurality of power meshes growing along a second direction, and defining an assistant connecting network on a third metal layer, wherein the assistant connecting network includes a plurality of assistant connecting lines growing along the second direction, the first plurality of power meshes are formed on a first metal layer, the second plurality of power meshes on a second metal layer, the third metal layer is below the first metal layer, and the second metal layer is above the first metal layer.	07-30-2009
20090193381	POWER MESH MANAGEMENT METHOD - The invention discloses a power mesh management method utilized in an integrated IC. The integrated circuit includes a macro block including at least a macro block power supplying line growing along a first direction. The management method includes: defining a plurality of first power supplying lines located in a metal layer above the macro block, wherein each of the first supplying lines grows along the first direction; defining a plurality of second power supplying lines located in another metal layer above the macro block, wherein each of the second supplying lines grows along a second direction; defining a partial power supplying line from the plurality of first power supplying lines where the partial power supplying line overlaps the macro block power supplying line; and removing the partial power supplying line from the plurality of first power supplying lines.	07-30-2009

Chia-Ming Chuang, Hsinchu City TW

Patent application number	Description	Published
20100200885	LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light emitting device and a method of fabricating thereof are provided. The method of fabricating the light emitting device comprises: providing a substrate having a first major surface and a second major surface; forming a plurality of light-emitting stacks on the first major surface; forming an etching protection layer on each of the light emitting stacks; forming a plurality of holes by a discontinuous laser beam on the substrate; etching the plurality of holes; and slicing off the substrate along the plurality of holes to form a light emitting device. The light emitting device has a substrate wherein the sidewall of the substrate comprising a first area with a substantially flat surface and a second area with substantially textured surface.	08-12-2010

Chi-Chih Chuang, Hsinchu City TW

Patent application number	Description	Published
20080293342	CMP HEAD AND METHOD OF MAKING THE SAME - A CMP head includes a membrane support and a membrane. The membrane support is disk-shaped, having an origin and a radius R. The membrane support has at least a ventilator disposed in a central region within the range between origin and (2/3) R, and at least a diversion opening disposed in a peripheral region within the range between (2/3) R and R. The membrane includes a disk-shaped part disposed on the first surface of the membrane support, and an annular part surrounding the annular sidewall of the membrane support.	11-27-2008

Chih-Chiang Chuang, Hsinchu City TW

Patent application number	Description	Published
20080252576	PANEL DISPLAY APPARATUS AND SOURCE DRIVER THEREOF - A panel display apparatus and a source driver including a set of first input terminals, a set of second input terminals, a set of first output terminals, a set of second output terminals, an interface module and a driving module are disclosed. The sets of the first and the second input terminals are coupled to a previous source driver and a timing controller, respectively. The sets of the first and the second output terminals are coupled to a following source driver and a display panel, respectively. The interface module selects the set of the first or the second input terminals upon a pre-setting, and connects the selected input terminals to the set of the first output terminals. The driving module generates at least a driving signal upon a signal of the selected input terminals. The driving signal is outputted to the display panel through the second output terminals.	10-16-2008
20080288261	METHOD FOR DYNAMICALLY ADJUSTING AUDIO DECODING PROCESS - A method for dynamically arranging DSP tasks. The method comprises receiving an audio bit stream, checking a remaining execution time as the DSP transforms the audio information into spectral information, simplifying the step of transforming the audio information when the DSP detects that the remaining execution time is shorter then a predetermined interval, and skipping one section of the audio information and decoding the remaining section when the execution time is less than a predetermined interval.	11-20-2008
20090040158	GAMMA REFERENCE VOLTAGE GENERATING DEVICE, METHOD FOR GENERATING GAMMA REFERENCE VOTLAGE, AND GRAY LEVEL VOLTAGE GENERATING DEVICE - A gamma reference voltage generating device, a method for generating gamma reference voltages, and a gray level voltage generating device are provided. The gray level voltage generating device includes a selection unit and a gray level voltage generator. The selection unit is adapted for receiving M first gamma reference voltages, and selecting N second gamma reference voltages from the M first gamma reference voltages and outputting the N second gamma reference voltages, wherein M and N are positive integers, and M>N. The gray level voltage generator is coupled to the selection unit, for generating a plurality of gray level voltages according to the N second gamma reference voltages. The gamma curve can be adaptively adjusted by using the present invention so as to improve the display quality.	02-12-2009
20090309860	Driving Method and Related Device for Reducing Power Consumption of LCD - A driving method is provided for reducing power consumption of a liquid crystal display. The driving method includes steps of sequentially receiving first data and second data, determining whether the second data is the same as the first data, and controlling a data-line driving circuit not to read in driving data corresponding to the second data when the second data is the same as the first data.	12-17-2009
20110099020	Method for Dynamically Adjusting Audio Decoding Process - A method for dynamically arranging DSP tasks. The method comprises receiving an audio bit stream, checking a remaining execution time as the DSP transforms the audio information into spectral information, simplifying the step of transforming the audio information when the DSP detects that the remaining execution time is shorter then a predetermined interval, and skipping one section of the audio information and decoding the remaining section when the execution time is less than a predetermined interval.	04-28-2011

Patent applications by Chih-Chiang Chuang, Hsinchu City TW

Ching-Sang Chuang, Hsinchu City TW

Patent application number	Description	Published
20100267177	METHOD FOR FABRICATING ACTIVE DEVICE ARRAY SUBSTRATE - A method for fabricating an active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is formed on the display area of the substrate. A gate insulator is formed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are formed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then formed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is formed on the passivation layer.	10-21-2010
20120112214	ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is disposed on the display area of the substrate. A gate insulator is disposed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are disposed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then disposed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is disposed on the passivation layer.	05-10-2012

Chin-Kai Chuang, Hsinchu City TW

Patent application number	Description	Published
20080274508	Expression system for enhancing solubility and immunogeneicity of recombinant proteins - Expression system for enhancing solubility and immunogenicity of recombinant proteins. The expression system includes a protein expression vector that contains a chimeric gene encoding a chimeric protein. The chimeric protein contains three polypeptidyl fragments: (a) a first polypeptidyl fragment at the N-terminal end of the chimeric protein that contains a protein transduction domain (PTD) or a fragment thereof having HIV Tat PTD activity; (b) a second polypeptidyl fragment at the C-terminal end of the first polypeptidyl fragment that contains a J-domain or a fragment thereof having heat shock protein 70 (Hsp70)-interacting activity; and (c) a third polypeptidyl fragment at the C-terminal end of the second polypeptidyl fragment that contains a target protein or polypeptide.	11-06-2008
20090187004	EXPRESSION SYSTEM FOR ENHANCING SOLUBILITY AND IMMUNOGENEICITY OF RECOMBINANT PROTEINS - Expression system for enhancing solubility and immunogenicity of recombinant proteins. The expression system includes a protein expression vector that contains a chimeric gene encoding a chimeric protein comprising: (a) a first polypeptidyl fragment at the N-terminal end of the chimeric protein, containing a protein transduction domain (PTD), or a fragment thereof, having HIV Tat PTD activity; (b) a second polypeptidyl fragment at the C-terminal end of the first polypeptidyl fragment, containing a J-domain, or a fragment thereof, having heat shock protein 70 (Hsp70)-interacting activity; and (c) a third polypeptidyl fragment at the C-terminal end of the second polypeptidyl fragment, containing a target protein or polypeptide.	07-23-2009

Fong-Lung Chuang, Hsinchu City TW

Patent application number	Description	Published
20080254619	METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. First, a semiconductor substrate and a dielectric layer positioned on the semiconductor substrate are prepared. Subsequently, the dielectric layer is etched to form a hole structure in the dielectric layer. Afterward, a degas process is performed. An ultraviolet (UV) treatment is carried out to the semiconductor substrate in the degas process so as to expel at least a gas contained in the dielectric layer. Next, a barrier layer is formed on the sidewall and on the bottom of the hole structure. Furthermore, the hole structure is filled with a conductive material. Since the UV treatment can degas the dielectric layer efficiently, the formed semiconductor device can have a fine and stable structure.	10-16-2008

Gene C.h. Chuang, Hsinchu City TW

Patent application number	Description	Published
20110158341	METHOD AND APPARATUS FOR PHASE QUANTIZATION AND EQUAL GAIN PRECODING USING LATTICES - A method and apparatus are disclosed for phase quantization and equal gain precoding in a wireless communication system. The method includes scaling, by a receiving device, a phase vector based on a predetermined scaling factor to determine a first lattice point. The method also includes determining, by the receiving device, a second lattice point based on the determined first lattice point. In addition, the method includes determining, by the receiving device, a quantized phase vector based on the determined second lattice point and the predetermined scaling factor.	06-30-2011
20120072151	ENERGY DETECTION METHOD AND AN ENERGY DETECTION CIRCUIT USING THE SAME - An energy detection method is provided. The method obtains an initial time point of an input signal with reference to a digital signal corresponding to the input signal. An i	03-22-2012

Harry Hak-Lay Chuang, Hsinchu City TW

Patent application number	Description	Published
20110042750	CONTROLLING GATE FORMATION FOR HIGH DENSITY CELL LAYOUT - Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a method includes forming a gate dielectric layer over a substrate, forming a gate electrode layer over the gate dielectric layer, and etching the gate electrode layer and the gate dielectric layer to form a horizontal gate structure and a vertical gate structure, wherein the horizontal gate structure and the vertical gate structure are connected by an interconnection portion. The method further includes forming a photoresist covering the horizontal gate structure and the vertical gate structure, with the photoresist having a gap exposing the interconnection portion between the horizontal gate structure and the vertical gate structure, and then etching the interconnection portion.	02-24-2011
20110057267	POLYSILICON DESIGN FOR REPLACEMENT GATE TECHNOLOGY - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.	03-10-2011
20110156142	HIGH VOLTAGE DEVICE WITH PARTIAL SILICON GERMANIUM EPI SOURCE/DRAIN - A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first type of conductivity, a lightly doped region formed in the substrate and aligned with a side of the gate structure, the lightly doped region having the first type of conductivity, and a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity.	06-30-2011
20110193161	METHOD AND APPARATUS OF FORMING A GATE - The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate and first and second wells that are disposed within the substrate. The first and second wells are doped with different types of dopants. The transistor includes a first gate that is disposed at least partially over the first well. The transistor further includes a second gate that is disposed over the second well. The transistor also includes source and drain regions. The source and drain regions are disposed in the first and second wells, respectively. The source and drain regions are doped with dopants of a same type.	08-11-2011
20110193162	LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR WITH PARTIALLY UNSILICIDED SOURCE/DRAIN - A method of fabricating a laterally diffused metal oxide semiconductor (LDMOS) transistor includes forming a dummy gate over a substrate. A source and a drain are formed over the substrate on opposite sides of the dummy gate. A first silicide is formed on the source. A second silicide is formed on the drain so that an unsilicided region of at least one of the drain or the source is adjacent to the dummy gate. The unsilicided region of the drain provides a resistive region capable of sustaining a voltage load suitable for a high voltage LDMOS application. A replacement gate process is performed on the dummy gate to form a gate.	08-11-2011
20110195549	GATE STACK FOR HIGH-K/METAL GATE LAST PROCESS - A method for fabricating an integrated circuit device is disclosed. An exemplary method includes providing a substrate; forming a high-k dielectric layer over the substrate; forming a first capping layer over the high-k dielectric layer; forming a second capping layer over the first capping layer; forming a dummy gate layer over the second capping layer; performing a patterning process to form a gate stack including the high-k dielectric layer, first and second capping layers, and dummy gate layer; removing the dummy gate layer from the gate stack, thereby forming an opening that exposes the second capping layer; and filling the opening with a first metal layer over the exposed second capping layer and a second metal layer over the first metal layer, wherein the first metal layer is different from the second metal layer and has a work function suitable to the semiconductor device.	08-11-2011
20110195557	METHOD FOR FORMING LOW RESISTANCE AND UNIFORM METAL GATE - The present disclosure provides a method that includes forming a high k dielectric layer on a semiconductor substrate; forming a polysilicon layer on the high k dielectric layer; patterning the high k dielectric layer and polysilicon layer to form first and second dummy gates in first and second field effect transistor (FET) regions, respectively; forming an inter-level dielectric (ILD); applying a first CMP process to the semiconductor substrate, exposing the first and second dummy gates; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a first metal electrode in the first gate trench; applying a second CMP process; forming a mask covering the first FET region and exposing the second dummy gate; thereafter removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a second metal electrode in the second gate trench; and applying a third CMP process.	08-11-2011
20110198675	SPACER STRUCTURE OF A FIELD EFFECT TRANSISTOR - This disclosure relates to a spacer structure of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate structure that has a sidewall overlying the substrate; a silicide region in the substrate on one side of the gate structure having an inner edge closest to the gate structure; a first oxygen-sealing layer adjoining the sidewall of the gate structure; an oxygen-containing layer adjoining the first oxygen-sealing layer on the sidewall and further including a portion extending over the substrate; and a second oxygen-sealing layer adjoining the oxygen-containing layer and extending over the portion of the oxygen-containing layer over the substrate, wherein an outer edge of the second oxygen-sealing layer is offset from the inner edge of the silicide region.	08-18-2011
20110201172	METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.	08-18-2011
20110210403	NOVEL STRUCTURES AND METHODS TO STOP CONTACT METAL FROM EXTRUDING INTO REPLACEMENT GATES - The methods and structures described are used to prevent protrusion of contact metal (such as W) horizontally into gate stacks of neighboring devices to affect the work functions of these neighboring devices. The metal gate under contact plugs that are adjacent to devices and share the (or are connected to) metal gate is defined and lined with a work function layer that has good step coverage to prevent contact metal from extruding into gate stacks of neighboring devices. Only modification to the mask layout for the photomask(s) used for removing dummy polysilicon is involved. No additional lithographical operation or mask is needed. Therefore, no modification to the manufacturing processes or additional substrate processing steps (or operations) is involved or required. The benefits of using the methods and structures described above may include increased device yield and performance.	09-01-2011
20110215404	Method and Apparatus of Forming ESD Protection Device - The present disclosure provides a semiconductor device having a transistor. The transistor includes a source region, a drain region, and a channel region that are formed in a semiconductor substrate. The channel region is disposed between the source and drain regions. The transistor includes a first gate that is disposed over the channel region. The transistor includes a plurality of second gates that are disposed over the drain region.	09-08-2011
20110215420	CASCODE CMOS STRUCTURE - A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.	09-08-2011
20110220963	METHOD AND APPARATUS OF FORMING BIPOLAR TRANSISTOR DEVICE - The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate. The transistor includes a collector region that is formed in a portion of the substrate. The transistor includes a base region that is surrounded by the collector region. The transistor includes an emitter region that is surrounded by the based region. The transistor includes an isolation structure that is disposed adjacent the emitter region. The transistor includes a gate structure that is disposed over a portion of the emitter region and a portion of the isolation structure.	09-15-2011
20110221009	METHOD AND APPARATUS FOR REDUCING GATE RESISTANCE - An apparatus has a semiconductor device that includes: a semiconductor substrate having a channel region, a high-k dielectric layer disposed at least partly over the channel region, a gate electrode disposed over the dielectric layer and disposed at least partly over the channel region, wherein the gate electrode is made substantially of metal, and a gate contact engaging the gate electrode at a location over the channel region. A different aspect involves a method for making a semiconductor device that includes: providing a semiconductor substrate having a channel region, forming a high-k dielectric layer at least partly over the channel region, forming a gate electrode over the dielectric layer and at least partly over the channel region, the gate electrode being made substantially of metal, and forming a gate contact that engages the gate electrode at a location over the channel region.	09-15-2011
20110227161	METHOD OF FABRICATING HYBRID IMPACT-IONIZATION SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device which includes a semiconductor substrate, a first gate structure disposed over the substrate, the first gate structure including a first gate electrode of a first conductivity type, a second gate structure disposed over the substrate and proximate the first gate structure, the second gate structure including a second gate electrode of a second conductivity type different from the first conductivity type, a first doped region of the first conductivity type disposed in the substrate, the first doped region including a first lightly doped region aligned with a side of the first gate structure, and a second doped region of the second conductivity type disposed in the substrate, the second doped region including a second lightly doped region aligned with a side of the second gate structure.	09-22-2011
20110227167	REDUCED SUBSTRATE COUPLING FOR INDUCTORS IN SEMICONDUCTOR DEVICES - The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate.	09-22-2011
20110237040	MAIN SPACER TRIM-BACK METHOD FOR REPLACEMENT GATE PROCESS - The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.	09-29-2011
20120001259	METHOD AND APPARATUS FOR IMPROVING GATE CONTACT - A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess.	01-05-2012
20120009754	METHOD FOR MAIN SPACER TRIM-BACK - The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.	01-12-2012
20120012937	INTERCONNECTION STRUCTURE FOR N/P METAL GATES - The disclosure relates to integrated circuit fabrication, and more particularly to an interconnection structure for N/P metal gates. An exemplary structure for an interconnection structure comprises a first gate electrode having a first portion of a first work-function metal layer under a first portion of a signal metal layer; and a second gate electrode having a second portion of the first work-function metal layer interposed between a second work-function metal layer and a second portion of the signal metal layer, wherein the second portion of the signal metal layer is over the second portion of the first work-function metal layer, wherein the second portion of the signal metal layer and the first portion of the signal metal layer are continuous, and wherein a maximum thickness of the second portion of the signal metal layer is less than a maximum thickness of the first portion of the signal metal layer.	01-19-2012
20120025309	OFFSET GATE SEMICONDUCTOR DEVICE - An offset gate semiconductor device includes a substrate and an isolation feature formed in the substrate. An active region is formed in the substrate substantially adjacent to the isolation feature. An interface layer is formed on the substrate over the isolation feature and the active region. A polysilicon layer is formed on the interface layer over the isolation feature and the active region. A trench being formed in the polysilicon layer over the isolation feature. The trench extending to the interface layer. A fill layer is formed to line the trench and a metal gate formed in the trench.	02-02-2012
20120025323	SPACER STRUCTURES OF A SEMICONDUCTOR DEVICE - The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width.	02-02-2012
20120032238	CONTACT ETCH STOP LAYERS OF A FIELD EFFECT TRANSISTOR - An exemplary structure for a field effect transistor according to at least one embodiment comprises a substrate comprising a surface; a gate structure comprising sidewalls and a top surface over the substrate; a spacer adjacent to the sidewalls of the gate structure; a first contact etch stop layer over the spacer and extending along the surface of the substrate; an interlayer dielectric layer adjacent to the first contact etch stop layer, wherein a top surface of the interlayer dielectric layer is coplanar with the top surface of the gate structure; and a second contact etch stop layer over the top surface of the gate structure.	02-09-2012
20120074475	METAL GATE STRUCTURE OF A SEMICONDUCTOR DEVICE - The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ⅔ of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ⅓ of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region.	03-29-2012
20120074498	METHOD AND APPARATUS FOR IMPROVING GATE CONTACT - A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess.	03-29-2012
20120083095	METHOD OF FABRICATING SEMICONDUCTOR DEVICE BY THINNING HARDMASK LAYERS ON FRONTSIDE AND BACKSIDE OF SUBSTRATE - The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.	04-05-2012
20120104471	CONTACT STRUCTURE FOR REDUCING GATE RESISTANCE AND METHOD OF MAKING THE SAME - A semiconductor device having a gate on a substrate with source/drain (S/D) regions adjacent to the gate. A first dielectric layer overlays the gate and the S/D regions, the first dielectric layer having first contact holes over the S/D regions with first contact plugs formed of a first material and the first contact plugs coupled to respective S/D regions. A second dielectric layer overlays the first dielectric layer and the first contact plugs. A second contact hole formed in the first and second dielectric layers is filled with a second contact plug formed of a second material. The second contact plug is coupled to the gate and interconnect structures formed in the second dielectric layer, the interconnect structures coupled to the first contact plugs. The second material is different from the first material, and the second material has an electrical resistance lower than that of the first material.	05-03-2012
20120119306	METAL GATE TRANSISTOR, INTEGRATED CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer.	05-17-2012

Hung-Yi Chuang, Hsinchu City TW

Patent application number	Description	Published
20080239610	CHIP SCALE GAS DISCHARGE PROTECTIVE DEVICE AND FABRICATION METHOD OF THE SAME - Disclosed is a chip scale gas discharge protective device whose metal coupled electrodes are fabricated through processes of yellow light, image formation, and electro-casting of metal electrode, and the two electrodes are facing each other in arch lines with the distance of a gap controlled within the range of 0.5˜10 μm, wherein the entire structure is performed by a bridge process without an extra gas filling procedure in the gap. Due to the fact that the gap is as small as only several μm, a relevant potential difference existing across there is sufficient to ionize the air thereby suppressing the electro-static discharge (ESD) through the protected electronic device, whereas the fabrication method is disclosed.	10-02-2008

Jen-Hui Chuang, Hsinchu City TW

Patent application number	Description	Published
20100157064	OBJECT TRACKING SYSTEM, METHOD AND SMART NODE USING ACTIVE CAMERA HANDOFF - If an active smart node detects that an object leaves a center region of a FOV for a boundary region, the active smart node predicts a possible path of the object. When the object gets out of the FOV, the active smart node predicts the object appears in a FOV of another smart node according to the possible path and a spatial relation between cameras. The active smart node notifies another smart node to become a semi-active smart node which determines an image characteristic similarity between the object and a new object and returns to the active smart node if a condition is satisfied. The active smart node compares the returned characteristic similarity, an object discovery time at the semi-active smart node, and a distance between the active smart node and the semi-active smart node to calculate possibility.	06-24-2010
20100290709	METHOD AND APPARATUS FOR RECOGNIZING TYPES OF VEHICLES - Consistent with the disclosed embodiments, the shapes of the windows of vehicles are used as features for recognizing vehicle types. This method transforms vehicle images with different view angles in a homographic manner to a normalized coordinate system and further extracts normalized window images. Subsequently, the method recognizes target vehicle types correctly in accordance with the normalized window images.	11-18-2010
20110044500	Light Information Receiving Method, Unit and Method for Recognition of Light-Emitting Objects - A light information receiving method, a method and a unit for the recognition of light-emitting objects are provided. The light information receiving method includes the following steps. A light-emitting object array is captured to obtain a plurality of images, wherein the light-emitting object array includes at least one light-emitting object. A temporal filtering process is performed to the images to recognize a light-emitting object. A light-emitting status of the light-emitting object array is recognized according to the light-emitting object location. A decoding process is performed according to the light-emitting status to output an item of information.	02-24-2011
20110102664	LIGHTING CONTROL MODULE, VIDEO CAMERA COMPRISING THE SAME AND CONTROL METHOD OF THE SAME - The present invention provides a lighting control module, a video camera comprising the same and a control method of the same. The video camera of the invention includes a sensing module, a light-emitting module and a control module. The sensing module receives a reflected light beam from a recording direction of the video camera, and generates an image of a scene in the recording direction. The light-emitting module emits a light toward the recording direction. Additionally, the lighting control module is connected to the light-emitting module for controlling the light-emitting module to periodically emit the light from a first brightness to a second brightness.	05-05-2011
20110118973	IMAGE PROCESSING METHOD AND SYSTEM - An image processing method and a system are provided. The image processing method of moving camera comprises the following steps. An image of a road is captured by a first camera unit. A coordinate of the image of an object shown in the image of the road is captured when the image of the object shown in the image of the road is selected. At least an aiming angle of a second camera unit is adjusted according to the coordinate to make the field-of-view of the second camera unit aligned with the object. The image of the object is captured by the second camera unit. The image of the object is enlarged.	05-19-2011

Jui Cheng Chuang, Hsinchu City TW

Patent application number	Description	Published
20120001054	SENSING DEVICE AND IMAGE SENSOR MODULE THEREOF - An image sensor module is installed in a sensing device, and is used to detect a reflected light of an object. The image sensor module includes a carrier, a light sensing element, and a package body. The light sensing element is disposed on a substrate. The carrier is disposed on the substrate in the sensing device. The light sensing element is installed in the carrier, and is electrically connected with the substrate via multiple solder balls. The package body is installed on the carrier, and has a reflecting and diverting element, which is located between the light sensing element and the object and is used for reflecting reflected light of the object and diverting the reflected light towards a receiving direction of the light sensing element. The light sensing element receives the reflected light and generates a corresponding sensing signal.	01-05-2012

Jung-Hong Chuang, Hsinchu City TW

Patent application number	Description	Published
20110122139	TWO DIMENSIONAL VECTOR GRAPHICS TRIANGULATION SYSTEM AND METHOD THEREOF - A two dimensional (2D) vector graphics triangulation system and a method thereof are provided. The system includes a memory module and a triangle mesh processing module. The memory module temporarily stores a triangle mesh triangulated from a 2D vector graphics into a binary tree data structure. The triangle mesh processing module adjusts the triangle mesh, or re-performs a triangulation processing to a local region of the loop when a state of a loop of the 2D vector graphics is changed. The triangle mesh processing module includes a level of detail unit, which proportionally adjusts an error threshold according to a zoom condition of the loop, updates an error value of each boundary line when the loop is deformed, and splits a boundary line or merges two neighbouring boundary lines according to the error values of the boundary lines and the error threshold.	05-26-2011

Ju Yuan Chuang, Hsinchu City TW

Patent application number	Description	Published
20110043033	Out-Door Unit with Multiple Ports - An out-door unit with multiple ports comprises a plurality of circuit blocks, a DC-DC converter and a plurality of ports. The DC-DC converter is configured to provide current to the plurality of circuit blocks. The plurality of ports is connected to a plurality of in-door units respectively via a diode and provides current from the plurality of in-door units to the DC-DC converter via a diode respectively. At least one of the plurality of ports is connected to a first circuit block of the plurality of circuit blocks to provide current to the first circuit block.	02-24-2011

Kai-Cheng Chuang, Hsinchu City TW

Patent application number	Description	Published
20110122086	TOUCH DISPLAY MODULE AND TOUCH DISPLAY APPARATUS COMPRISING THE SAME - A touch display apparatus comprising a controller and a touch display module, electrically connected to the controller, are provided. The touch display module comprises a display panel and a sensor assembly. The display panel includes a display surface and a connection surface opposite the display surface, and the sensor assembly is disposed on the connection surface and electrically connected to the controller. The sensor assembly comprises a first sensing layer and a second sensing layer, with a first sheet conducting layer and a second sheet conducting layer, respectively. When the display surface is touched, the first sheet conducting layer and the second sheet conducting layer are electrically connected to generate a touch signal. Thereby, the controller may detect a touch position according to the touch signal.	05-26-2011
20110175872	DISPLAY DEVICE FOR CONVERTING BETWEEN BRIGHT AND DARK STATES AND METHOD THEREOF - The configurations and controlling methods of a display device are provided in the present invention. The proposed display device having an environmental brightness, a display content and a display background with a display brightness includes a light sensor sensing the environmental brightness and adjusting the display brightness according to the environmental brightness such that a reader could read the display content easily.	07-21-2011
20110279385	TOUCH DISPLAY APPARATUS AND ELECTRONIC READING APPARATUS WITH TOUCH INPUT FUNCTION - The present invention relates to a touch display apparatus, which is including a display unit and a touch unit installed under the display unit. The display unit includes a first substrate and a second substrate installed in parallel. The touch unit includes a third substrate installed under the second substrate in parallel, and a plurality of first electrodes and a plurality of second electrodes separately installed on the lower surface of the second substrate and on the upper surface of the third substrate and facing each other. When a user touches the display unit of the electronic reading apparatus, the display unit will have a local deformation accordingly, the first electrode and the second electrode touch each other, and thus a touch signal is generated. Therefore, a touch function can be achieved.	11-17-2011
20110285733	DIGITAL STICKY NOTE WITH ELECTRIC PAPER DISPLAY - A digital sticky note has an electric paper displayer having a substrate. In addition, a display is configured on the substrate for showing an image picture without power. Further, a wireless receiver module, a process unit and a display circuit are also configured on the substrate. Wherein, the wireless receiver module receives a memo information through a wireless transmission interface, and transmits the memo information to the processor unit. Therefore, the processor unit controls the display circuit to show the memo information on the display array according to the obtained memo information.	11-24-2011
20120036088	Price display apparatus having bistable display panel and method thereof - The configurations of a price display apparatus and a method thereof are provided in the present invention. The proposed price display apparatus includes a bistable display panel displaying a selling price of an item.	02-09-2012
20120038598	ELECTROPHORETIC DISPLAY APPARATUS AND METHOD FOR MANUFACTURING THE SAME AND METHOD FOR DRIVING THE SAME - An electrophoretic display device includes an electrophoretic displaying layer, a photoconductive layer and a top electrode layer. The electrophoretic displaying layer includes a number of pixels. The top electrode layer and the photoconductive layer are respectively disposed at two opposite sides of the electrophoretic displaying layer. The photoconductive layer includes a number of photoconductive units spaced apart from each other. Each of the pixels corresponds to at least one photoconductive units. The present invention also provides a method for manufacturing the electrophoretic display device and a method for driving the electrophoretic display device.	02-16-2012

Keng-Han Chuang, Hsinchu City TW

Patent application number	Description	Published
20110199763	LIGHT COMBINATION DEVICE - A light combination device includes a reflective element and a first color separating element. The reflective element guides first color light beams emitted from at least a first light source and a second light source to propagate in a first direction. The first light source and the second light source are differently positioned in a space. The first color separating element transmits the first color light beams and reflects second color light beams emitted from at least a third light source and a fourth light source. The third light source and the fourth light source are differently positioned in the space. The first color separating element has a coating curved surface, and a curvature of the coating curved surface is varied according to positions of the third light source and the fourth light source to guide the second color light beams to propagate in the first direction.	08-18-2011

Li-Heng Chuang, Hsinchu City TW

Patent application number	Description	Published
20090129437	PROBE COVER FOR EAR THERMOMETER AND MANUFACTURING METHOD THEREOF - The present invention provides a probe cover for an ear thermometer and a manufacturing method thereof. The probe cover is for sheathing a measuring probe of the ear thermometer, and an engaging means is provided at a bottom of the measuring probe. The probe cover comprises a main body of a hollow structure, an abutting segment and a base. Therein, the main body has an open end and a closed end opposite to the open end. An assembling direction extending from the open end toward the closed end is where the measuring probe is assembled along. Further, the main body has a diameter gradually reducing along the assembling direction. The closed end allows infrared rays to be received by the measuring probe to pass therethrough. Therein, the abutting segment is provided at the open end of the main body, and the base is annularly provided around a periphery of the abutting segment. The probe cover is characterized in being integrally formed, and having an annular shoulder provided at the abutting segment for accommodating the engaging means of the ear thermometer, as well as a plurality of separated protuberances, which are formed inwardly at a combining portion between the abutting segment and the base, for being engaged with the engaging means of the ear thermometer so that the probe cover can be firmly engaged with the measuring probe.	05-21-2009

Meng-Ju Chuang, Hsinchu City TW

Patent application number	Description	Published
20100195017	ELECTRONIC DEVICE, LIQUID CRYSTAL DISPLAY MODULE, BACKLIGHT UNIT, AND FRONT FRAME THEREOF - The invention provides an electronic device including a liquid crystal display module and a control circuit. The liquid display module includes a backlight unit and a liquid display panel. The backlight unit has a front frame which includes a plastic frame and a conductive line. The conductive line extends from the rear surface to the rear surface to the front surface of the plastic frame so as to form a contact on the front surface.	08-05-2010

Patent applications by Meng-Ju Chuang, Hsinchu City TW

Min Lun Chuang, Hsinchu City TW

Patent application number	Description	Published
20080238479	REVERSIBLE SEQUENTIAL ELEMENT AND REVERSIBLE SEQUENTIAL CIRCUIT THEREOF - A reversible sequential element comprises a first logic gate and a second logic gate. The first logic gate includes a first input terminal, a second input terminal, a third input terminal, a first output terminal coupled to the first input terminal, a second output terminal and a third output terminal. The second logic gate includes a first input line, a second input line, a first output line and a second output line. When the first input terminal is set to a first state, the second input terminal is coupled to the third output terminal and the third input terminal is coupled to the second output terminal; otherwise, the second input terminal is coupled to the second output terminal and the third input terminal is coupled to the third output terminal. The third output terminal, second input line and second output line are coupled to each other. The input signal carried on the first input line is set as 0 so that the second output line and the first output line have the same output.	10-02-2008

Sheng-Yi Chuang, Hsinchu City TW

Patent application number	Description	Published
20100045206	LED Driving Circuit - An LED driving circuit to provide DC power to an LED to generate light includes a voltage-lowering regulation circuit, a rectification circuit and a filter and current-limiting circuit. The voltage-lowering regulation circuit aims to regulate impedance and provide a back electromotive force with polarity opposite to input voltage so that input power passed through the voltage-lowering regulation circuit is offset by the back electromotive force to a lower voltage. Then the input power passes through the rectification circuit to become DC power. The filter and current-limiting circuit receives the DC power and has at least one filter element to absorb or release the voltage to perform filtering and at least one current-limiting resistor to limit DC value. Therefore, the DC power has a steady voltage and current to energize the LED for lighting.	02-25-2010
20100314808	METHOD FOR MANUFACTURING LAMP SHELL - A method for manufacturing lamp shell to improve structural strength and light penetration includes steps of: providing a plastic material, injecting the plastic material into a injection molding equipment to form a preform containing a first space with an opening and a connecting section at one end and a closed another end to form a light penetrating section, and placing the preform in a blow molding equipment and blowing the plastic material by injecting gas to inflate the preform through gas pressure to form a second space at a greater size than the first space to become a lamp shell. The lamp shell thus formed has a greater structural strength to meet safety requirements, and also provides improved light penetration, and can reduce material consumption of the lamp shell to save production cost.	12-16-2010
20110156583	LED LAMP SET AND LIGHTING BULB OF THE SAME - An LED lamp set and a lighting bulb used thereon are provided. The LED lamp set comprises a plurality of circuit boards, a support post, an ignition circuit and two conducting wires. The circuit boards are spaced from each other in a parallel manner and mounted on the support post in series. Each of the circuit boards is connected to a plurality of LEDs surrounding the support post. The LEDs have a plurality of light emission surfaces tilted outwards. The ignition circuit receives an input power and transforms the input power to an ignition power. The two conducting wires have one end connected to the ignition circuit and linked to the circuit boards in series to ignite the LEDs. The LED lamp set further is coupled with a socket and a lamp shade to form a profile of a lighting bulb compatible to the socket of the ordinary lighting bulbs.	06-30-2011
20110248631	LED LAMP SET - An LED lamp set includes a socket connecting to electric power, an ignition circuit board held in the socket to form electric connection therewith and a lamp assembly controlled by the ignition circuit board. The lamp assembly includes a stem and a plurality of LED substrates fastened to the stem. The stem has a plurality of troughs formed on the circumference and a plurality of spacers to separate the troughs. The stem further has an upper holding portion at the upper circumference to form a retaining space with the troughs and a sealed lower side connecting to a circuit board. The circuit board and the ignition circuit board are electrically connected. Each LED substrate has at least a portion wedged in the retaining space and is electrically connected to a plurality of LEDs. The LED substrate has an electric connection portion electrically connected to the circuit board.	10-13-2011

Shiao-Cheng Chuang, Hsinchu City TW

Patent application number	Description	Published
20090239809	Process For Preparing Peptide Products For Promoting Cholecystokinin Secretion And Use Of The Peptide Products - A process for producing a peptide product having cholecystokinin secretion promoting effect, said process comprising hydrolyzing soybean residues with one or more proteases so that the peptide product having cholecystokinin secretion promoting effect is obtained. Also disclosed is the composition containing the peptide product and the use thereof.	09-24-2009

Shih-Chang Chuang, Hsinchu City TW

Patent application number	Description	Published
20110144467	FLEXIBLE 3D MICROPROBE STRUCTURE - The present invention discloses a flexible 3D microprobe structure, which comprises at least one probe, a base and a hinge portion. The probe is connected to the base via the hinge portion. The probe forms a bend angle with respect to a normal of the base by attracting the probe through an electrostatic force to make the hinge portion bend with respect to the base, and thus to form a 3D structure having the bend angle. The probe, the base and the hinge portion are made of a flexible polymeric material to reduce the inflammation response of creatures. Further, a fixing element is used to enhance the structural strength of the flexible 3D microprobe structure.	06-16-2011

Tzu-Sou Chuang, Hsinchu City TW

Patent application number	Description	Published
20090275278	ULTRA-PURE AIR SYSTEM FOR NANO WAFER ENVIRONMENT - In one embodiment, an air filtration system includes a first ventilation path connected between at least one external air supply and a clean room. The first ventilation path is configured to direct air from the at least one external air supply to the clean room. A second ventilation path is connected to the clean room. The second ventilation path is configured to recirculate air in the clean room. A third ventilation path, separate from the first path, is connected between the at least one external air supply and a tool environment disposed within the clean room. The third ventilation path includes an ultra-pure air filtration unit disposed between the outdoor air supply and the tool environment. The ultra-pure air filtration unit includes a compressor and a dryer.	11-05-2009

Wei-Shun Chuang, Hsinchu City TW

Patent application number	Description	Published
20120137264	MULTIPLE LEVEL SPINE ROUTING - Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a net comprising a set of pins, a first wire for routing the net is generated, the set of pins comprising the net is partitioned into one or more groups based at least in part on a cost function, a second wire that connects to the first wire is generated for each group of the net, and a third wire that connects each pin to the second wire of its group is generated for each pin of each group of the net.	05-31-2012
20120137265	MULTIPLE LEVEL SPINE ROUTING - Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a plurality of nets and a specification of a set of routing tracks available for main spines, a main spine routing track is assigned to each of the plurality of nets based at least in part on a cost function and main spine wires are generated on the assigned main spine routing tracks for each of the plurality of nets.	05-31-2012

Ying-Ting Chuang, Hsinchu City TW

Patent application number	Description	Published
20110296073	TIME ALIGNING CIRCUIT AND TIME ALIGNING METHOD FOR ALIGNING DATA TRANSMISSION TIMING OF A PLURALITY OF LANES - A time aligning circuit includes a plurality of buffers, a plurality of delay selectors, a plurality of adjustment symbol generators, and a controller. Each buffer receives an ordered set on a corresponding lane. Each delay selector delays an output of the ordered set of the corresponding buffer. Each adjustment symbol generator outputs an adjustment symbol or the output received from the corresponding delay selector according to an adjustment control signal. When an initial symbol of a designated delay selector is detected but initial symbols of other delay selectors are not received yet, the controller generates the delay control signal to the designated delay selector and generates the adjustment control signal to control a designated adjustment symbol generator corresponding to the designated delay selector in order to output one adjustment symbol until initial signals of all delay selectors are detected.	12-01-2011

Yu-Chun Chuang, Hsinchu City TW

Patent application number	Description	Published
20080204293	MULTI-CHANNEL DISPLAY DRIVER CIRCUIT INCORPORATING MODIFIED D/A CONVERTERS - A multi-channel display driver circuit incorporating modified D/A converters has a plurality of digital comparators connected to a number generator. Each digital comparator has an output, a digital data input and a reference input. The reference inputs of all digital comparators are connected to the number generator and the outputs are respectively connected to corresponding data channels of a display. By the proposed technique, each digital comparator obtains a unique non-sequence reference signal, and then compares it with the input digital data signal. Since the non-sequential signals are input to the reference input of the digital comparator, the overshoot distortion, the harmonic distortion and the electromagnetic interference problems are prevented. Therefore, the precise imaging can be obtained with this signal modulation technique in small circuit size.	08-28-2008

Yueh-Lin Chuang, Hsinchu City TW

Patent application number	Description	Published
20120128059	Method of adaptive motion estimation in search windows for video coding - The invention discloses a method of adaptive motion estimation in search windows for video coding, which uses adjacent MBs to predict the range of search window, storing MVs of adjacent MBs respectively for each reference frame, then using MVs of three adjacent MBs to delimit the scope of search window on the same reference frame. It could derive the most similar MB from the scope of search window than the current MB.	05-24-2012

Yu-Min Chuang, Hsinchu City TW

Patent application number	Description	Published
20080292009	MULTIPLE-INPUT-MULTIPLE-OUTPUT WIRELESS TRANSMISSION SYSTEM AND TRANSMISSION METHOD THEREOF - The present invention relates to a multiple-input-multiple-output (MIMO) wireless transmission system and a transmission method thereof. A wireless transmitting system thereof receives encoded data via a first processing unit, which processes the encoded data and outputs the encoded data to a plurality of modulation units for modulating the encoded data to produce a plurality of modulated data. A plurality of first conversion units converts the plurality of modulated data to a plurality of transmitting signals. A plurality of radio-frequency (RF) circuits receives the plurality of transmitting signals and transmits RF signals according to the frequency-hopping sequence of a piconet. A plurality of receiving processing units of a wireless receiving system according to the present invention receives the RF signals, respectively, according to the frequency-hopping sequence of the piconet and transmits to a plurality of second conversion units for converting the RF signals to received data. A switching circuit switches the received data according to the frequency-hopping sequence of the piconet. A plurality of demodulation units demodulates the switched received data to produce demodulated data. A second processing unit received the demodulated data, and processes the demodulated data to output demodulated data. A decoding unit decodes the demodulated data output by the second processing unit to produce output data.	11-27-2008

Yung-Hui Chuang, Hsinchu City TW

Patent application number	Description	Published
20100163105	SOLAR CELL PACKAGE TYPE WITH SURFACE MOUNT TECHNOLOGY STRUCTURE - A solar cell package type with surface mount technology structure, comprising: a solar cell having a first electric terminal at the bottom thereof and a second electric terminal at the top thereof; at least a connection electric terminal capped at both sides of the solar cell in such a way that the top of the connection electric terminal is connected to the second electric terminal; and at least an insulation layer capped at both sides and partially placed at the bottom of the solar cell in such a way that it is interposed between the electric terminal and the solar cell for avoiding the short current and the water penetration. In this way, this package in accordance with the invention tends to increase the array density of the solar cells on the substrate and to minimize the manufacturing cost.	07-01-2010

Yung-Sheng Chuang, Hsinchu City TW

Patent application number	Description	Published
20110122086	TOUCH DISPLAY MODULE AND TOUCH DISPLAY APPARATUS COMPRISING THE SAME - A touch display apparatus comprising a controller and a touch display module, electrically connected to the controller, are provided. The touch display module comprises a display panel and a sensor assembly. The display panel includes a display surface and a connection surface opposite the display surface, and the sensor assembly is disposed on the connection surface and electrically connected to the controller. The sensor assembly comprises a first sensing layer and a second sensing layer, with a first sheet conducting layer and a second sheet conducting layer, respectively. When the display surface is touched, the first sheet conducting layer and the second sheet conducting layer are electrically connected to generate a touch signal. Thereby, the controller may detect a touch position according to the touch signal.	05-26-2011

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