Patent application number | Description | Published |
20100112737 | METHOD FOR FORMING PIXEL STRUCTURE OF TRANSFLECTIVE LIQUID CRYSTAL DISPLAY DEVICE - A forming method of the present invention includes forming a first patterned conductive layer, which includes a transparent conductive layer and a metal layer stacked together on a substrate, where the first patterned conductive layer functions as gate lines, gate electrodes, common lines and predetermined transparent pixel electrode structures; and forming a second patterned conductive layer on the substrate. The second patterned conductive layer includes data lines and reflective pixel electrodes, and be directly connected to doping regions, such as source regions/drain regions. According to the forming method of the present invention, pixel structures of a transflective liquid crystal display device can be formed through five mask processes. Therefore, the manufacturing process of the transflective liquid crystal display device is effectively simplified, so the product yield is improved and the cost can be reduced. | 05-06-2010 |
20100207033 | X-RAY DETECTOR AND FABRICATION METHOD THEREOF - A structure of X-ray detector includes a Si-rich dielectric material for serving as a photo-sensing layer to increase light sensitivity. The fabrication method of the X-ray detector including the Si-rich dielectric material needs less photolithography-etching processes, so as to reduce the total thickness of thin film layers and decrease process steps and cost. | 08-19-2010 |
20130196475 | Transistor with Etching Stop Layer and Manufacturing Method Thereof - This invention provides a transistor with an etching stop layer and a manufacturing method thereof. The transistor structure includes a substrate, a crystalline semiconductor layer, an etching stop structure, an ohmic contact layer, a source, a drain, a gate insulating layer, and a gate. The manufacturing method is performed by patterning the ohmic contact layer and the crystalline semiconductor layer at the same time with the same mask; and patterning the ohmic contact layer and the source/drain layer at the same time with another the same mask. | 08-01-2013 |
Patent application number | Description | Published |
20150318188 | Substrate Pad Structure - A structure comprises a plurality of top pads protruding over a top surface of a package substrate, wherein a top pad comprises a first half-circle portion, a second half-circle portion and a first rectangular portion between the first half-circle portion and the second half-circle portion, a plurality of bottom pads embedded in the package substrate, wherein a bottom pad comprises a third half-circle portion, a fourth half-circle portion and a second rectangular portion between the third half-circle portion and the fourth half-circle portion and a plurality of vias coupled between the top pads and their respective bottom pads. | 11-05-2015 |
20150371964 | Bonded Structures for Package and Substrate - The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance. | 12-24-2015 |
20160027752 | Elongated Bump Structures in Package Structure - A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d | 01-28-2016 |
20160064347 | Bump on Pad (BOP) Bonding Structure - The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints. | 03-03-2016 |
20160079192 | Metal Routing Architecture for Integrated Circuits - A device includes a substrate, a metal pad over the substrate, and a metal trace electrically disconnected from the metal pad. The metal pad and the metal trace are level with each other. A passivation layer includes a portion overlapping an edge portion of the metal pad. A metal pillar is overlying the metal pad, and is electrically connected to the metal pad. The metal trace has a portion overlapped by the metal pillar. | 03-17-2016 |
Patent application number | Description | Published |
20080305599 | Gate Control and Endcap Improvement - A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode layer. The gate electrode layer and dielectric layer are etched thereby forming gate structures and dummy patterns, wherein at least one of the dummy patterns has at least a portion in the active region. The first photo resist is removed. A second photo resist is formed covering the gate structures. The dummy patterns unprotected by the second photo resist are removed. The second photo resist is then removed. | 12-11-2008 |
20100078695 | Low Leakage Capacitors Including Portions in Inter-Layer Dielectrics - An integrated circuit structure includes a semiconductor substrate including a first region and a second region; an insulation region in the second region of the semiconductor substrate; and an inter-layer dielectric (ILD) over the insulation region. A transistor is in the first region. The transistor includes a gate dielectric and a gate electrode over the gate dielectric. A first conductive line and a second conductive line are over the insulation region. The first conductive line and the second conductive line are substantially parallel to each other and extending in a first direction. A first metal line and a second metal line are in a bottom metal layer (M | 04-01-2010 |
20100155783 | Standard Cell Architecture and Methods with Variable Design Rules - Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at least one portion spaced from a cell boundary by a first spacing distance of less than half of the minimum spacing distance; a second standard cell disposed adjacent the first standard cell with at least one second portion of the conductive layer in the second cell disposed adjacent the first portion in the first standard cell and spaced apart from a common cell boundary by a second spacing greater than half of the minimum; wherein the sum of the first and second spacings is at least as great as the minimum spacing. A method for forming standard is disclosed. | 06-24-2010 |
20100159685 | Eliminating Poly Uni-Direction Line-End Shortening Using Second Cut - A method of forming an integrated circuit structure includes providing a substrate including a first active region and a second active region; forming a gate electrode layer over the substrate; and etching the gate electrode layer. The remaining portions of the gate electrode layer include a first gate strip and a second gate strip substantially parallel to each other; and a sacrificial strip unparallel to, and interconnecting, the first gate strip and the second gate strip. The sacrificial strip is between the first active region and the second active region. The method further includes forming a mask layer covering portions of the first gate strip and the second gate strip, wherein the sacrificial strip and portions of the first gate strip and the second gate strip are exposed through an opening in the mask layer; and etching the sacrificial strip and the portions of the first gate strip and the second gate strip through the opening. | 06-24-2010 |
20100285643 | Modifying Work Function in PMOS Devices by Counter-Doping - A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode. | 11-11-2010 |
20110076813 | Semiconductor Device with both I/O and Core Components and Method of Fabricating Same - A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated. | 03-31-2011 |
20110177658 | Standard Cell Architecture and Methods with Variable Design Rules - Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at least one portion spaced from a cell boundary by a first spacing distance of less than half of the minimum spacing distance; a second standard cell disposed adjacent the first standard cell with at least one second portion of the conductive layer in the second cell disposed adjacent the first portion in the first standard cell and spaced apart from a common cell boundary by a second spacing greater than half of the minimum; wherein the sum of the first and second spacings is at least as great as the minimum spacing. A method for forming standard is disclosed. | 07-21-2011 |
20110183506 | Eliminating Poly Uni-Direction Line-End Shortening Using Second Cut - A method of forming an integrated circuit structure includes providing a substrate including a first active region and a second active region; forming a gate electrode layer over the substrate; and etching the gate electrode layer. The remaining portions of the gate electrode layer include a first gate strip and a second gate strip substantially parallel to each other; and a sacrificial strip unparallel to, and interconnecting, the first gate strip and the second gate strip. The sacrificial strip is between the first active region and the second active region. The method further includes forming a mask layer covering portions of the first gate strip and the second gate strip, wherein the sacrificial strip and portions of the first gate strip and the second gate strip are exposed through an opening in the mask layer; and etching the sacrificial strip and the portions of the first gate strip and the second gate strip through the opening. | 07-28-2011 |
20110227189 | Dishing-Free Gap-Filling with Multiple CMPs - A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed. | 09-22-2011 |
20110233682 | Reducing Device Performance Drift Caused by Large Spacings Between Active Regions - A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting. | 09-29-2011 |
20110260251 | Semiconductor Device and Method of Fabricating Same - A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated. | 10-27-2011 |
20110284972 | Modifying Work Function in PMOS Devices by Counter-Doping - A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode. | 11-24-2011 |
Patent application number | Description | Published |
20110193794 | Touch Display Panel - A touch display panel includes a display panel, a second substrate, at least a first spacer and at least a touch sensing unit. The display panel includes a first substrate and a plurality of display units. The first substrate includes a display surface and a non-display surface, and the display units are disposed on the display surface. The second substrate is disposed opposite to the first substrate and is disposed on a side of the non-display surface of the first substrate. The first spacer is disposed between the first substrate and the second substrate to maintain a distance therebetween. The touch sensing unit includes a sensing conductive pad and a conductive unit, wherein a gap is disposed between the sensing conductive pad and the conductive unit. | 08-11-2011 |
20110298753 | OPTICAL TOUCH PANEL AND TOUCH DISPLAY PANEL AND TOUCH INPUT METHOD THEREOF - An optical touch panel includes a substrate, a single planar light generator, at least a retro reflector device, and a single photo sensor array. The substrate has a surface. The single planar light generator is disposed outside the surface of the substrate for generating a planar light, where the illuminating range of the planar light covers the range of the surface of the substrate. The retro reflector device is disposed on a side of the substrate for reflecting the planar light. The single photo sensor array is disposed outside the surface of the substrate for sensing the reflected planar light and generating reflected light distribution information. | 12-08-2011 |
20120133598 | TOUCH DISPLAY DEVICE - A touch display device includes a display panel, a light guide plate, at least an invisible light emitting device, and a first light path converting device. The light guide plate includes a plurality of microstructures to reflect an invisible light generated by the invisible light emitting device such that the invisible light passes through the display panel, reaching the first light path converting device. | 05-31-2012 |
20120170315 | Three-Dimensional Display Apparatus and Backlight Module Thereof - A three-dimensional display apparatus and a backlight module thereof are provided. The display apparatus further includes a display panel disposed on the backlight module. The backlight module has a light guide plate, a plurality of microstructures, a first light source, and a second light source. The light guide plate has a bottom surface and a light emitting surface opposite to the bottom surface, wherein the microstructures are disposed on at least one of the two surfaces. The first light source is at a first corner of the light guide plate while the second light source is at a second corner opposite to the first corner. A first surface and a second surface of the microstructure define an orientation direction (or form a distribution direction) along or parallel to the diagonal line through the first and second corners. | 07-05-2012 |
Patent application number | Description | Published |
20110012009 | IMAGE SENSOR - An image sensor includes a light-sensing element, a first transistor, and a second transistor. The light-sensing element has a first end and a second end electrically connected to a select line. The first transistor has a first end electrically connected to a first control line, a control end electrically connected to the first end, and a second end electrically connected to the first end of the light-sensing element. The second transistor has a first end electrically connected to a voltage source, a control end electrically connected to the first end of the light-sensing element, and a second end electrically connected to an output line. The light-sensing element uses the material of silicon rich oxide so that the light-sensing element can sense the luminance variance and have the characteristic of the capacitor for the level boost. | 01-20-2011 |
20130062509 | IMAGE SENSOR - An image sensor includes a light-sensing element, a first transistor, and a second transistor. The light-sensing element has a first end and a second end electrically connected to a select line. The first transistor has a first end electrically connected to a first control line, a control end electrically connected to the first end, and a second end electrically connected to the first end of the light-sensing element. The second transistor has a first end electrically connected to a voltage source, a control end electrically connected to the first end of the light-sensing element, and a second end electrically connected to an output line. The light-sensing element uses the material of silicon rich oxide so that the light-sensing element can sense the luminance variance and have the characteristic of the capacitor for the level boost. | 03-14-2013 |
20140098014 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display panel includes a pixel array, a first shift register, M first output cells, a second shift register, and N second output cells. The first register is disposed on a first side of the pixel array. The M first output cells are coupled to and next to the first shift register for providing M gate signals to M rows of the pixel array according to a first clock signal. The second register is disposed on a second side of the pixel array. The N second output cells are coupled to and next to the second shift register for providing N gate signals to N rows of the pixel array according to a second clock signal. M and N are positive integers. | 04-10-2014 |
20150179277 | SHIFT REGISTER - A shift register has an input stage circuit, a first switch, a control circuit and a pull down circuit. A first end of the first switch receives a first clock signal. A second end and a control end of the first switch are respectively coupled to an output end of the shift register and a first output end of the input stage circuit. The control circuit controls electrical connection between a first power terminal and a node according to a second clock signal and controls electrical connection between the node and a second power terminal according to a voltage level of a second output end of the input stage circuit. The pull down circuit controls electrical connection between the second output end and the second power terminal and electrical connection between the output end and the second power terminal according to a voltage level of the node. | 06-25-2015 |
20150206597 | SHIFT REGISTER AND CONTROL METHOD THEREOF - A shift register has a first switch, a pull-up circuit, and a pull-down circuit. The first switch receives a first clock signal. The pull-up circuit is configured to turn on the first switch to pull up a voltage level of an output terminal of the shift register. The pull-up circuit has a second switch and a first control circuit. The first control circuit is coupled to a first system power terminal to avoid an excessive voltage difference between two nodes of the first control circuit. The pull-down circuit is configured to pull down the voltage level of the output terminal of the shift register when the first switch is turned off, and further configured to keep a voltage level of a control node of a switch coupled between the output terminal and a second system power terminal at a low voltage. | 07-23-2015 |
20150228243 | DISPLAY PANEL, GATE DRIVER AND CONTROL METHOD - A display panel, a gate driver and a control method are disclosed herein. The gate driver includes series-coupled driving stages. One of the driving stages includes an input unit and a shift register circuit. The input unit outputs a shift signal to a control node according to a gate driving signal from the previous driving stage and the gate driving signal from the next driving stage. The shift register circuit is electrically coupled to the control node, and outputs the gate driving signal. During the enabling period of the gate driving signal from the previous driving stage and the enabling period of the gate driving signal from the current driving stage, the shift register circuit keeps the voltage level of the control node being at a first voltage. | 08-13-2015 |
Patent application number | Description | Published |
20090001939 | APPARATUS FOR PREVENTING CAPACITOR CHARGER FROM OVERCHARGING AND METHOD THEREOF - An apparatus for controlling a charging circuit is provided. The apparatus includes a first detector, a second detector, and a controller. The first detector detects a voltage level at a first time and generates a first indication value corresponding to the voltage level at the first time, where the voltage level corresponds to an output voltage of the charging circuit. The second detector detects the voltage level at a second time after the first time and generates a second indication value corresponding to the voltage level at the second time. The controller receives the first and second indication values, and generates a control signal according to the first and second indication values for turning the charging circuit on and off. | 01-01-2009 |
20090115390 | POWER CONVERTER WITH PROTECTION MECHANISM FOR DIODE IN OPEN-CIRCUIT CONDITION AND PULSE-WIDTH-MODULATION CONTROLLER THEREOF - A power converter with a protection mechanism for a diode in an open-circuit condition includes a DC to Dc (DC/DC) conversion circuit, a detection and protection circuit, a pulse-width-modulation (PWM) signal generator, and a logic gate. The detection and protection circuit is used for detecting an open-circuit condition of the diode of the DC/DC conversion circuit. The logic gate receives an output signal of the detection and protection circuit and a PWM signal outputted by the PWM signal generator. When the diode is in an open-circuit condition, the PWM signal cannot be transmitted to a power switch of the DC/DC conversion circuit due to the output signal of the detection and protection circuit. | 05-07-2009 |
20090121674 | CHARGING DEVICE WITH BOUNDARY MODE CONTROL - A charging device with boundary mode control is disclosed. The charging device includes a transformer, a power switch, a detection circuit and a pulse-width modulation (PWM) controller. The power switch is electrically connected to one end of a primary-side winding of the transformer. The detection circuit is electrically connected to the primary-side winding and the power switch. The detection circuit detects the resonance of the parasitic capacitance of the power switch, thereby generating a detection signal for boundary mode control. The PWM controller generates a pulse-width modulation signal for driving the power switch, and turns on the power switch according to the detection signal. | 05-14-2009 |
20090147548 | CONTROL CIRCUIT FOR ADJUSTING LEADING EDGE BLANKING TIME AND POWER CONVERTING SYSTEM USING THE SAME CONTROL CIRCUIT - A control circuit for adjusting leading edge blanking time is disclosed. The control circuit is applied to a power converting system. The control circuit adjusts a leading edge blanking time according to a feedback signal relative to a load connected to the output terminal of the power converting system. An over-current protection mechanism of the power converting system is disabled within the leading edge blanking time. | 06-11-2009 |
20100026268 | CONTROL METHOD FOR ADJUSTING LEADING EDGE BLANKING TIME IN POWER CONVERTING SYSTEM - A control method for adjusting leading edge blanking time in a power converting system is disclosed. The control method includes: receiving a feedback signal relative to a load connected to an output terminal of the power converting system; determining the leading edge blanking time to be a first value if the feedback signal has a magnitude about a first voltage; and determining the leading edge blanking time to be a second value if the feedback signal has a magnitude about a second voltage, wherein the first value is smaller than the second value, and the first voltage is greater than the second voltage. | 02-04-2010 |
20100142231 | Control Methods and Integrated Circuits for Controlling Power Supply - Integrated circuits for controlling power supplies and relevant control methods are disclosed. A controller generates a control signal to control a power switch. A feedback pin of an integrated circuit receives an external feedback signal representing an output voltage signal of a power supply. Controlled by the control signal, a transferring circuit transfers the feedback signal to the controller when the power switch is off. When the power switch is on, a clamping circuit clamps the voltage of the feedback signal at a predetermined value to avoid the controller from being influenced by the feedback signal. | 06-10-2010 |
20110133714 | POWER CONVERTER WITH PROTECTION MECHANISM FOR DIODE IN OPEN-CIRCUIT CONDITION AND PULSE-WIDTH-MODULATION CONTROLLER THEREOF - A power converter with a protection mechanism for a diode in an open-circuit condition includes a DC to Dc (DC/DC) conversion circuit, a detection and protection circuit, a pulse-width-modulation (PWM) signal generator, and a logic gate. The detection and protection circuit is used for detecting an open-circuit condition of the diode of the DC/DC conversion circuit. The logic gate receives an output signal of the detection and protection circuit and a PWM signal outputted by the PWM signal generator. When the diode is in an open-circuit condition, the PWM signal cannot be transmitted to a power switch of the DC/DC conversion circuit due to the output signal of the detection and protection circuit. | 06-09-2011 |
20110141778 | SWITCH CONTROLLER FOR SWITCHING POWER SUPPLY AND METHOD THEREOF - A switch controller for switching power supply is coupled to an auxiliary winding of the switching power supply through a detecting resistor. The switch controller provides a detecting current passing through the detecting resistor for keeping the voltage level of a detecting signal transmitted by the detecting resistor higher than a predetermined voltage. In this way, the switch controller can avoid the latch-up phenomenon caused by receiving the detecting signal of the negative voltage level. In addition, the switch controller can detect the magnitude of an input voltage of the switching power supply by means of the detecting current, and accordingly control the operation of the switching power supply. | 06-16-2011 |
20130307606 | SUPER HIGH VOLTAGE DEVICE AND METHOD FOR OPERATING A SUPER HIGH VOLTAGE DEVICE - A super high voltage device includes a first gate, a second gate, a drain, a first source, a second source, and a third source. The first gate is used for receiving a first control signal generated from a pulse width modulation controller. The second gate is used for receiving a second control signal generated from the pulse width modulation controller. The drain is used for receiving an input voltage. First current flowing from the drain to the first source varies with the first control signal and the input voltage. The second control signal is used for controlling turning-on and turning-off of second current flowing from the drain to the second source and third current flowing from the drain to the third source. The third source is proportional to the second current. | 11-21-2013 |
Patent application number | Description | Published |
20130258613 | TOUCH PANEL AND TOUCH DISPLAY PANEL - A touch panel includes a substrate, a transparent sensor electrode pattern, a patterned compensation electrode, a passivation layer, a transparent shielding electrode and at least one connection structure. The substrate has a surface and includes a sensor region and a peripheral region. The transparent sensor electrode pattern is disposed on the surface of the substrate and in the sensor region. The patterned compensation electrode is disposed on the surface of the substrate and in the peripheral region, and the patterned compensation electrode and the transparent sensor electrode pattern are electrically isolated. The passivation layer is disposed on the surface of the substrate, covers the transparent sensor electrode pattern, and at least partially exposes the patterned compensation electrode. The transparent shielding electrode is disposed on the passivation layer. The connection structure is electrically connected to the transparent shielding electrode and the patterned compensation electrode exposed by the passivation layer. | 10-03-2013 |
20150092306 | Panel Device Having Electrostatic Discharge Protection - A display device includes a substrate, at least one signal circuit, a ground protection circuit, and an auxiliary protection circuit. The substrate has a first surface, wherein the first surface includes an active area and a frame area surrounding the active area. The at least one signal circuit is disposed and extending along the frame area and electrically coupled to the active area. The ground protection circuit is disposed and extending along the frame area, wherein the ground protection circuit is positioned at a side of the signal circuit facing an edge of the substrate. The auxiliary protection circuit is disposed and extending along the frame area. The auxiliary protection circuit is disposed between the signal circuit and the ground protection circuit, wherein the auxiliary protection circuit respectively has a gap with the signal circuit and the ground protection circuit, and is electrically conductive. | 04-02-2015 |
20150234520 | TOUCH PANEL, TOUCH DISPLAY PANEL AND TOUCH SIGNAL SENSING METHOD - A touch panel includes a substrate, a sensing array, a plurality of first connection lines and at least two button sensing pads. The substrate has an active region and a peripheral region disposed on at least one side of the active region. The sensing array is disposed in the active region, which includes a plurality of first sensing electrode series disposed in the active region along a first direction and a plurality of second sensing electrode series disposed in the active region along a second direction. The first and second sensing electrode series intersect and form a plurality of sensing units. The first connection lines are disposed in the peripheral region and electrically connected to the first sensing electrode series respectively. The at least two button sensing pads are disposed in the peripheral region, and electrically connected to at least two first connection lines respectively to form a virtual button. | 08-20-2015 |
Patent application number | Description | Published |
20120270369 | Methods for Lead Free Solder Interconnections for Integrated Circuits - Methods for forming lead free solder interconnections for integrated circuits. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of material is formed on the input/output terminal of the integrated circuit. A lead free solder connector is formed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. An intermetallic compound is formed at the interface between the cap layer and the lead free solder connector. A solder connection is formed between input/output terminal of the integrated circuit and the metal finish pad that is less than 0.5 weight percent copper, and the intermetallic compound is substantially free of copper. | 10-25-2012 |
20130270699 | Conical-Shaped or Tier-Shaped Pillar Connections - A pillar structure for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled. | 10-17-2013 |
20130288473 | Electrical Connection Structure - A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer. | 10-31-2013 |
20130320524 | Design Scheme for Connector Site Spacing and Resulting Structures - A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. | 12-05-2013 |
20140035148 | Bump on Pad (BOP) Bonding structure - The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints. | 02-06-2014 |
20140048929 | Bonded Structures for Package and Substrate - The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance. | 02-20-2014 |
20140070402 | Stress Reduction Apparatus - A structure comprises a plurality of connectors formed on a top surface of a first semiconductor die, a second semiconductor die formed on the first semiconductor die and coupled to the first semiconductor die through the plurality of connectors and a first dummy conductive plane formed between an edge of the first semiconductor die and the plurality of connectors, wherein an edge of the first dummy conductive plane and a first distance to neutral point (DNP) direction form a first angle, and wherein the first angle is less than or equal to 45 degrees. | 03-13-2014 |
20140117534 | Interconnection Structure - A structure comprises a first passivation layer formed over a substrate, a second passivation layer formed over the first passivation layer, wherein the second passivation layer includes a first opening with a first dimension, a bond pad embedded in the first passivation layer and the second passivation layer, a protection layer formed on the second passivation layer comprising a second opening with a second dimension, wherein the second dimension is greater than the first dimension and a connector formed on the bond pad. | 05-01-2014 |
20140124947 | Methods and Apparatus for Flip Chip Substrate with Guard Rings Outside of a Die Attach Region - Methods and apparatus for flip chip substrates with guard rings. An embodiment comprises a substrate core with a die attach region for attaching an integrated circuit die; at least one dielectric layer overlying a die side surface of the substrate core; and at least one guard ring formed adjacent a corner of the substrate core, the at least one guard ring comprising: a first trace overlying the dielectric layer having rectangular portions extending in two directions from the corner of the substrate core and in parallel to the edges of the substrate core; a second trace underlying the dielectric layer; and at least one via extending through the dielectric layer and coupling the first and second traces; wherein the first trace, the at least one via, and the second trace form a vertical via stack. Methods for forming the flip chip substrates with the guard rings are disclosed. | 05-08-2014 |
20140159203 | Substrate Pad Structure - A structure comprises a first pad protruding over a top surface of a package substrate, wherein the first pad is of a first elongated shape, a second pad embedded in the package substrate, wherein the second pad is of a second elongated shape and a via coupled between the first pad and the second pad. | 06-12-2014 |
20140191390 | Metal Routing Architecture for Integrated Circuits - A device includes a substrate, a metal pad over the substrate, and a metal trace electrically disconnected from the metal pad. The metal pad and the metal trace are level with each other. A passivation layer includes a portion overlapping an edge portion of the metal pad. A metal pillar is overlying the metal pad, and is electrically connected to the metal pad. The metal trace has a portion overlapped by the metal pillar. | 07-10-2014 |
20140191391 | ELONGATED BUMP STRUCTURES IN PACKAGE STRUCTURE - A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis. In an embodiment, L is greater than d1, and W is less than d2. | 07-10-2014 |
20140231987 | Connector Structures of Integrated Circuits - A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad. | 08-21-2014 |
20140231994 | APPARATUS FOR LEAD FREE SOLDER INTERCONNECTIONS FOR INTEGRATED CIRCUITS - An apparatus includes an integrated circuit having at least one input/output terminal comprising copper formed thereon. A metal cap layer overlies an upper surface of the at least one input/output terminal. A substrate includes at least one conductive trace formed on a first surface, and a metal finish layer overlies a portion of the at least one conductive trace. A lead free solder connection is disposed between the metal cap layer and the metal finish layer, and a first intermetallic compound is disposed at an interface between the metal cap layer and the lead free solder connection. The lead free solder connection has a copper content of less than 0.5 wt. %, and the first intermetallic compound is substantially free of copper. | 08-21-2014 |
20140377946 | Bonded Structures for Package and Substrate - The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance. | 12-25-2014 |
20150303160 | Connector Structures of Integrated Circuits - A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad. | 10-22-2015 |
20150318188 | Substrate Pad Structure - A structure comprises a plurality of top pads protruding over a top surface of a package substrate, wherein a top pad comprises a first half-circle portion, a second half-circle portion and a first rectangular portion between the first half-circle portion and the second half-circle portion, a plurality of bottom pads embedded in the package substrate, wherein a bottom pad comprises a third half-circle portion, a fourth half-circle portion and a second rectangular portion between the third half-circle portion and the fourth half-circle portion and a plurality of vias coupled between the top pads and their respective bottom pads. | 11-05-2015 |
20150371964 | Bonded Structures for Package and Substrate - The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance. | 12-24-2015 |
20160027752 | Elongated Bump Structures in Package Structure - A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d | 01-28-2016 |
20160064347 | Bump on Pad (BOP) Bonding Structure - The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints. | 03-03-2016 |
20160079192 | Metal Routing Architecture for Integrated Circuits - A device includes a substrate, a metal pad over the substrate, and a metal trace electrically disconnected from the metal pad. The metal pad and the metal trace are level with each other. A passivation layer includes a portion overlapping an edge portion of the metal pad. A metal pillar is overlying the metal pad, and is electrically connected to the metal pad. The metal trace has a portion overlapped by the metal pillar. | 03-17-2016 |
Patent application number | Description | Published |
20120162181 | DISPLAY PANEL, PIXEL CIRCUIT AND DRIVING METHOD OF DIFFERENTIAL VOLTAGE DRIVEN DEVICE THEREIN - A display panel, a pixel circuit and a driving method of a differential voltage driving device are disclosed. The driving method includes: respectively supplying an alternating common voltage in a first polarity and a first display data in a second polarity to two terminals of the differential voltage driven device in a first frame; disconnecting the differential voltage driven device from the alternating common voltage, thereby keeping one terminal of the differential voltage driving device at the first polarity of the alternating common voltage; converting the alternating common voltage to the second polarity in a second frame which is consecutive to the first frame; and respectively supplying the alternating common voltage in the second polarity and a second display data in the first polarity to the two terminals of the differential voltage driving device in the second frame, here the first polarity is inverse to the second polarity. | 06-28-2012 |
20120169694 | LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF - A liquid crystal display includes a first switch for outputting a first electrode voltage according to a first data signal and a first gate signal, a second switch for outputting a second electrode voltage according to a second data signal and the first gate signal, a liquid crystal capacitor for controlling liquid-crystal transmittance according to the difference between the first and second electrode voltages, a first storage capacitor for storing the first electrode voltage, a third switch, a second storage capacitor for storing the second electrode voltage, and a fourth switch. The third switch controls the operation of furnishing a first common voltage to the first storage capacitor according to a second gate signal, for adjusting the first electrode voltage. The fourth switch controls the operation of furnishing a second common voltage to the second storage capacitor according to the second gate signal, for adjusting the second electrode voltage. | 07-05-2012 |
20130002640 | DRIVING CIRCUIT OF A PIXEL OF A LIQUID CRYSTAL DISPLAY PANEL AND DRIVING METHOD THEREOF - A driving circuit of a pixel includes a driving capacitor for driving liquid crystals according to a voltage difference between first and second ends of the driving capacitor, a reference voltage source for providing a reference voltage, a first data line for providing a first driving voltage, a second data line for providing a second driving voltage, a first scan circuit for electrically connecting the first and the second data lines to the first and the second ends of the driving capacitor respectively when the first scan circuit is turned on, a first scan line for controlling on and off states of the first scan circuit, a second scan circuit for electrically connecting the first end and the second end of the driving capacitor when the second scan circuit is turned on, and a second scan line for controlling on and off states of the second scan circuit. | 01-03-2013 |