| Patent application number | Description | Published |
|---|
| 20090066367 | INPUT OUTPUT DEVICE FOR MIXED-VOLTAGE TOLERANT - An input output device coupled between a core circuit and a pad and including an output cell, an input cell, and a pre-driver. The output cell includes an output stage and a voltage level converter. The output stage includes a first transistor and a second transistor connected to the first transistor in serial between a first supply voltage and a second voltage. The voltage level converter generates a first gate voltage to the first transistor according to the first voltage and a data signal. When the first supply voltage is increased, the first gate voltage is increased. When the data signal is at a high level, the first transistor is turned on. The input cell includes a pull unit and a first N-type transistor. The pre-driver turns off the first and the second transistors. | 03-12-2009 |
| 20090108870 | I/O BUFFER CIRCUIT - An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit ( | 04-30-2009 |
| 20100097117 | Mixed-voltage I/O buffer - A mixed-voltage input/output (I/O) buffer includes an output buffer circuit. The output buffer circuit includes an output stage circuit, a gate-tracking circuit and a floating N-well circuit. The output stage circuit includes stacked pull-up P-type transistors and stacked pull-down N-type transistors, in which a first P-type transistor of the stacked pull-up P-type transistors and a first N-type transistor of the stacked pull-down N-type transistors are coupled to an I/O pad. The gate-tracking circuit controls gate voltage of the first P-type transistor in accordance with a voltage of the I/O pad to prevent leakage current. The floating N-well circuit provides N-well voltages for an N-well of the first P-type transistor and an N-well of a second P-type transistor, controlling gate voltage of the first P-type transistor, of the gate-tracking circuit to prevent leakage current. | 04-22-2010 |
| 20100141324 | Mixed-Voltage Tolerant I/O Buffer and Output Buffer Circuit Thereof - An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second determining signals and a first and a second bias voltages according to the power supply voltage. The dynamic gate bias generating circuit is biased by the first and the second bias voltages and receives the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals. The pad voltage detector detects a voltage of an I/O pad and provides a pad voltage detecting signal for the output stage circuit to modify an output signal outputted to an I/O pad. A mixed-voltage input/output (I/O) buffer is disclosed herein. | 06-10-2010 |
| 20100168828 | IMPLANTABLE BIOMEDICAL CHIP WITH MODULATOR FOR A WIRELESS NEURAL STIMULATION SYSTEM - The invention relates to an implantable biomedical chip with modulator for a wireless neural stimulating system. The implantable biomedical chip comprises a power regulator, a demodulator, a baseband circuit, a D/A converter, an instrumentation amplifier, an A/D converter and a modulator. According to the invention, the modulator is mounted on the implantable biomedical chip, and can achieve full-duplex communication to improve the controllability and observability. Besides, the power consumption and area occupation is reduced as compared with using discrete components. Therefore, the integration of the implantable biomedical chip can be easily accomplished. | 07-01-2010 |
| 20100277216 | I/O Buffer Circuit - An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit ( | 11-04-2010 |
| 20110026175 | ELECTROSTATIC DISCHARGE PROTECTING CIRCUIT WITH ULTRA-LOW STANDBY LEAKAGE CURRENT FOR TWICE SUPPLY VOLTAGE TOLERANCE - The invention relates to an electrostatic discharge protecting circuit with ultra-low standby leakage current for twice supply voltage tolerance. The electrostatic discharge protecting circuit of the invention includes a substrate driver, a third transistor, a start-up circuit, a RC circuit and a second resistor. The substrate driver has a first transistor and a second transistor in serious connection. The start-up circuit has a fourth transistor and a fifth transistor with diode-connected. The RC circuit has a first resistor, a sixth transistor and a seventh transistor in serious connection. Compared with the prior art, the electrostatic discharge protecting circuit with ultra-low standby leakage current for twice supply voltage tolerance of the invention with advantages of low standby leakage current, high ESD robustness, and no gate-oxide reliability issue is an excellent circuit solution for on-chip ESD protection design for mixed-voltage I/O buffers in nanometer CMOS technologies. | 02-03-2011 |
