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Chu, Kaohsiung County

Fu-Shun Chu, Kaohsiung County TW

Patent application numberDescriptionPublished
20090094606Method for fast XSL transformation on multithreaded environment - An XSLT method is used in a multi-thread environment. In the XSLT method, an XML file is analyzed in view of XSLT templates. Relationships between the transforming processes of the XSLT templates and the tree nodes of the XML file are built. Time for the execution of the transforming process of each of the XSLT templates and the number of a related one of the tree nodes are calculated. Threads are scheduled for the transforming processes of the XSLT templates. The transforming processes of the XSLT templates are executed.04-09-2009

Kuo-Chang Chu, Kaohsiung County TW

Patent application numberDescriptionPublished
20080217296ETCHING APPARATUS FOR SEMICONDUCTOR PROCESSING APPARATUS AND METHOD THEREOF FOR RECYCLING ETCHANT SOLUTIONS - An etching apparatus of a semiconductor processing apparatus and the method thereof for recycling etchant solutions are provided. The method is suitable for a processing apparatus which provides an etchant solution on a wafer so as to perform an etching process. After the etching process is completed, a water solution is added to the etchant solution for maintaining a water content thereof. Then, the mixed etchant solution is recycled.09-11-2008

Ming-Tsai Chu, Kaohsiung County TW

Patent application numberDescriptionPublished
20110052553STRAIN OF LACTOBACILLUS PLANTARUM LP28 AND ITS USE IN TREATING HYPERSENSITIVITY REACTIONS - A new strain of 03-03-2011

Pin-Chien Chu, Kaohsiung County TW

Patent application numberDescriptionPublished
20090108291SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device including a gate structure, two doped regions, and two buffer layers is provided. The gate structure is disposed on a substrate. The two doped regions are made of boron doped silicon germanium (SiGeB) and are disposed in the substrate at both sides of the gate structure. The two buffer layers are made of carbon doped silicon germanium (SiGeC) and are respectively disposed between the two doped regions and the substrate.04-30-2009
20100032715MOS TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate. Next, the spacer is thinned, and epitaxial layer is grown in each of the two recesses. By thinning the spacer before the epitaxial layer is formed, the present invention could stop the epitaxial layer to grow against the sidewall of the spacer, thereby preventing problem such as Ion degradation.02-11-2010
20110086479METHOD FOR SELECTIVE FORMATION OF TRENCH - A method for selective formation of trenches is disclosed. First, a substrate is provided. The substrate includes a first semiconductor element and a second semiconductor element. The first semiconductor element has a dopant. Second, a wet etching procedure is carried out to selectively form a pair of trenches in the substrate around the second semiconductor element, a first source/drain ion implantation is selectively carried out on the first semiconductor element, or a second source/drain ion implantation is selectively carried out on the second semiconductor element.04-14-2011

Patent applications by Pin-Chien Chu, Kaohsiung County TW

Wen-Chung Chu, Kaohsiung County TW

Patent application numberDescriptionPublished
20090194737LIQUID CRYSTAL ALIGNMENT SOLUTION - A liquid crystal alignment solution is provided. The liquid crystal alignment solution includes a first polyimide-polyamide acid and a second polyimide-polyamide acid. The first polyimide-polyamide acid is represented by formula (A),08-06-2009
20100243955LIQUID CRYSTAL ALIGNMENT SOLUTION - A liquid crystal alignment solution is provided. The liquid crystal alignment solution includes at least one polymer selected from the group consisting of a polyamide acid-polyamide acid polymer represented by formula (A), a polyimide-polyamide acid polymer represented by formula (B) and a polyimide-polyimide polymer represented by formula (C),09-30-2010

Wen-Ting Chu, Kaohsiung County TW

Patent application numberDescriptionPublished
20100041194SEMICONDUCTOR DEVICE WITH SPLIT GATE MEMORY CELL AND FABRICATION METHOD THEREOF - A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell.02-18-2010

Patent applications by Wen-Ting Chu, Kaohsiung County TW

Yu-Ren Chu, Kaohsiung County TW

Patent application numberDescriptionPublished
20100295160QUAD FLAT PACKAGE STRUCTURE HAVING EXPOSED HEAT SINK, ELECTRONIC ASSEMBLY AND MANUFACTURING METHODS THEREOF - A quad flat package (QDP) structure having an exposed heat sink is provided. The QDP structure includes a leadframe, a chip, a heat sink, an insulating layer and a molding compound. The leadframe includes a die pad and multiple leads surrounding the die pad. The chip is disposed on the die pad and electrically connected to the die pad and the leads. The heat sink has a top surface, a bottom surface opposite thereto, and a side surface connected to the top and the bottom surfaces. The die pad is disposed in a central area of the top surface of the heat sink and electrically connected to the heat sink. The molding compound encapsulates the chip, the die pad, an inner lead portion of each lead and heat sink, and exposes the bottom surface of the heat sink and an outer lead portion of each lead.11-25-2010