Patent application number | Description | Published |
20090101915 | PHOTO SENSOR AND FABRICATION METHOD THEREOF - A photo sensor includes a patterned shielding conductive layer disposed on a transparent substrate, and a buffer dielectric layer, a patterned semiconductor layer, and a dielectric layer disposed on the patterned shielding layer in order. The patterned semiconductor layer includes an intrinsic region, a first doped region, and a second doped region, wherein the first and second doped regions are positioned at two sides of the intrinsic region separately. A patterned transparent conductive layer is disposed on the dielectric layer and covers the boundary of the intrinsic region and the first doped region and the boundary of the intrinsic region and the second doped region. The patterned transparent conductive layer is electrically connected to the patterned shielding conductive layer. | 04-23-2009 |
20090242959 | Flash Memory Cell - A flash memory cell is disclosed in the specification and drawing. The flash memory cell is described and shown with at least one floating gate heavily doped with P-type ions. | 10-01-2009 |
20090283772 | PHOTO SENSITIVE UNIT AND PIXEL STRUCTURE AND LIQUID CRYSTAL DISPLAY PANEL HAVING THE SAME - A pixel structure suitable for being disposed on a substrate is provided. The pixel structure includes a display unit and a photo sensitive unit. The display unit includes an active device and a pixel electrode. The active device is disposed on the substrate, and the pixel electrode is electrically connected to the active device. The photo sensitive unit includes a photocurrent readout unit, a shielding electrode, a photosensitive dielectric layer, and a transparent electrode. The shielding electrode is electrically connected to the photocurrent readout unit, and the photosensitive dielectric layer is disposed on the shielding electrode. The transparent electrode is disposed on the photosensitive dielectric layer that is interposed between the shielding electrode and the transparent electrode. | 11-19-2009 |
20090289920 | OPTICAL REFLECTED TOUCH PANEL AND PIXELS AND SYSTEM THEREOF - An optical reflective touch panel and pixels and a system thereof are provided. Each pixel of the optical reflective touch panel includes a display circuit and a sensing circuit. The display circuit controls the display of the pixel. The sensing circuit is coupled to the display circuit for sensing a sensitization state of the pixel during a turned-on period and a turned-off period of a backlight module and outputting a digital signal to notify an optical reflective touch panel system that whether the pixel is touched or not. | 11-26-2009 |
20090323387 | One-Time Programmable Memory and Operating Method Thereof - A one-time programmable memory cell is provided, the one-time programmable memory cell comprises: a gate dielectric layer disposed on a well; a gate electrode disposed on the gate dielectric layer; source/drain regions disposed in the well at the sides of the gate electrode, respectively; a first salicide layer disposed on one of the source/drain regions; a capacitive dielectric layer disposed on the gate electrode and the other of the source/drain regions; a first conductive plug disposed on the first salicide layer; and a second conductive plug disposed on the capacitive dielectric layer. The size of the first conductive plug is different form the size of the second conductive plug. | 12-31-2009 |
20110026297 | VARIABLE AND REVERSIBLE RESISTIVE ELEMENT, NON-VOLATILE MEMORY DEVICE AND METHODS FOR OPERATING AND MANUFACTURING THE NON-VOLATILE MEMORY DEVICE - A variable and reversible resistive element includes a transition metal oxide layer, a bottom electrode and at least one conductive plug module. The bottom electrode is disposed under the transition metal oxide layer. The conductive plug module is disposed on the transition metal oxide layer. The conductive plug module includes a metal plug and a barrier layer. The conductive plug is electrically connected with the transition metal oxide layer. The barrier layer surrounds the metal plug, wherein the transition metal oxide layer is made by reacting a portion of a dielectric layer being directly below the metal plug and a portion of the barrier layer contacting the portion of the dielectric layer, wherein the dielectric layer is formed on the bottom electrode. Moreover, a non-volatile memory device and methods for operating and manufacturing the same is disclosed in specification. | 02-03-2011 |
20110165727 | METHOD OF FABRICATING PHOTO SENSOR - A method of fabricating a photo sensor includes the following steps. First, a substrate is provided, having a conductive layer, a buffer dielectric layer, a patterned semiconductor layer, a dielectric layer, and a planarization layer disposed thereon from bottom to top, wherein the patterned semiconductor layer comprises a first doped region, an intrinsic region, and a second doped region disposed in order. Then, the planarization layer is patterned to form an opening in the planarization layer to expose a portion of the dielectric layer, wherein the opening is positioned on the intrinsic region and portions of the first and the second doped regions. Thereafter, at least a patterned transparent conductive layer is formed in the opening, covering the boundary of the intrinsic region and the first doped region and the boundary of the intrinsic region and the second doped region. | 07-07-2011 |
20110210385 | Non-volatile Semiconductor Device, Programmable Memory, Capacitor and Metal Oxide Semiconductor - A non-volatile semiconductor device, a programmable memory device, a capacitor and a metal oxide semiconductor are disclosed, wherein the non-volatile semiconductor device includes a gate dielectric layer, a floating gate, a coupling gate, a source and a drain. The gate dielectric layer is formed on a semiconductor substrate. The floating gate is formed on the gate dielectric layer. The source and the drain are formed in the semiconductor substrate and are disposed at opposing sides of the floating gate. The coupling gate consists essentially of a capacitor dielectric layer and a contact plug, where the capacitor dielectric layer is formed on the floating gate, and the contact plug is formed on the capacitor dielectric layer. | 09-01-2011 |
20110233654 | NANO-CRYSTAL GATE STRUCTURE FOR NON-VOLATILE MEMORY - A non-volatile memory device is disclosed having a charge storage layer that incorporates a plurality of nano-crystals. A substrate having a source region and a drain region is provided. Select and control gates are formed on the substrate. The charge storage layer is provided between the control gate and the substrate. The nano-crystals in the charge storage layer have a size of about 1 nm to about 10 nm, and may be formed of Silicon or Germanium. Writing operations are accomplished via hot electron injection, FN tunneling, or source-side injection. Erase operations are accomplished using FN tunneling. The control gate is formed of a single layer of polysilicon, which reduces the total number of processing steps required to form the device, thus reducing cost. | 09-29-2011 |
20120091424 | NON-VOLATILE MEMORY DEVICE AND METHODS FOR MANUFACTURING THE SAME - A variable and reversible resistive element includes a transition metal oxide layer, a bottom electrode and at least one conductive plug module. The bottom electrode is disposed under the transition metal oxide layer. The conductive plug module is disposed on the transition metal oxide layer. The conductive plug module includes a metal plug and a barrier layer. The conductive plug is electrically connected with the transition metal oxide layer. The barrier layer surrounds the metal plug, wherein the transition metal oxide layer is made by reacting a portion of a dielectric layer being directly below the metal plug and a portion of the barrier layer contacting the portion of the dielectric layer, wherein the dielectric layer is formed on the bottom electrode. Moreover, a non-volatile memory device and methods for operating and manufacturing the same is disclosed in specification. | 04-19-2012 |
20120257458 | NON-VOLATILE SEMICONDUCTOR DEVICE, AND METHOD OF OPERATING THE SAME - A non-volatile semiconductor device and a method for operating the same are disclosed, where the non-volatile semiconductor device includes a gate dielectric layer, a n-type floating gate, a coupling gate, a first n-type source/drain, a second n-type source/drain, a first contact plug and a second contact plug. The gate dielectric layer is formed on a p-type semiconductor substrate. The n-type floating gate is formed on the gate dielectric layer. The first n-type source/drain and the second n-type source/drain are formed in the p-type semiconductor substrate. The first and second contact plugs are formed on the first and second n-type source/drains respectively. The coupling gate consists essentially of a capacitor dielectric layer and a third contact plug, where the capacitor dielectric layer is formed on the n-type floating gate, and the third contact plug is formed on the capacitor dielectric layer. | 10-11-2012 |
20120314509 | NON-VOLATILE SEMICONDUCTOR DEVICE, AND METHOD OF OPERATING THE SAME - A non-volatile semiconductor device and a method for operating the same are disclosed, where the non-volatile semiconductor device includes a gate dielectric layer, a p-type floating gate, a coupling gate, a first p-type source/drain, a second p-type source/drain, a first contact plug and a second contact plug. The gate dielectric layer is formed on a n-type semiconductor substrate. The p-type floating gate is formed on the gate dielectric layer. The first p-type source/drain and the second p-type source/drain are formed in the n-type semiconductor substrate. The first and second contact plugs are formed on the first and second p-type source/drains respectively. The coupling gate consists essentially of a capacitor dielectric layer and a third contact plug, where the capacitor dielectric layer is formed on the p-type floating gate, and the third contact plug is formed on the capacitor dielectric layer. | 12-13-2012 |
20130126820 | VARIABLE AND REVERSIBLE RESISTIVE MEMORY STORAGE ELEMENT AND MEMORY STORAGE MODULE HAVING THE SAME - A variable and reversible resistive memory storage element and a memory storage module having the same are provided. The memory storage module comprises a select gate element and the resistive memory storage element. The select gate element comprises two source/drain regions. The resistive memory storage module comprises a first electrode, a first high-k dielectric layer and a second electrode. The first electrode is a semiconductor doping area, which is one of the two source/drain regions of the select gate element. The first high-k dielectric layer is formed on the first electrode to provide a variable resistance. The second electrode is a first metal gate formed on the first high-k dielectric layer. | 05-23-2013 |
20150063038 | MEMORY CELL, MEMORY ARRAY AND OPERATION METHOD THEREOF - A memory cell, a memory array and an operation method are disclosed herein. The memory cell includes a substrate with a first conductivity type, a first doped region with a second conductivity type, a second doped region with the second conductivity type, a first floating gate, a second floating gate and a word gate. The first and the second doped region are disposed in the substrate. The first floating gate is disposed on the substrate and electrically coupled to the first doped region. The second floating gate is disposed on the substrate and electrically coupled to the second doped region. The word line gate is disposed on the substrate and between the first and second doped region, wherein the word gate includes a first part extending over the first floating gate and a second part extending over the second floating gate. | 03-05-2015 |
20150076581 | MEMORY ARRAY AND NON-VOLATILE MEMORY DEVICE OF THE SAME - A non-volatile memory device is provided. The non-volatile memory device includes a substrate area, two storage units, a spacer structure and two control units. The storage units include two anti-fuse gates each having a gate dielectric layer between the anti-fuse gate and the substrate area and two diffusion areas. The spacer structure is formed on the substrate area and between the two anti-fuse gates and contacts thereto. Each of the diffusion areas is a first doping area doped with a first type dopant contacting one of the two anti-fuse gates. Each of the control units includes a select gate formed on the substrate area and a second doping area. A first side of the select gate contacts one of the diffusion areas of the storage unit. The second doping area is doped with the first type dopant and contacts a second side of the select gate. | 03-19-2015 |