Patent application number | Description | Published |
20090166757 | STRESS ENGINEERING FOR SRAM STABILITY - A design structure embodied in a machine readable medium is provided for use in the design, manufacturing, and/or testing of Ics that include at least one SRAM cell. In particular, the present invention provides a design structure of an IC embodied in a machine readable medium, the IC including at least one SRAM cell with a gamma ratio of about 1 or greater. In the present invention, the gamma ratio is increased with degraded pFET device performance. Moreover, in the inventive IC, there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides a design structure of an IC embodied in a machine readable medium, the IC comprising at least one static random access memory cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the at least one nFET and the at least one pFET. | 07-02-2009 |
20100078687 | Method for Transistor Fabrication with Optimized Performance - A semiconductor process and apparatus includes forming <100> channel orientation CMOS transistors ( | 04-01-2010 |
20100244198 | CMOS SIGE CHANNEL PFET AND SI CHANNEL NFET DEVICES WITH MINIMAL STI RECESS - Silicon germanium (SiGe) is epitaxially grown on a silicon channel above nFET and pFET regions of a substrate. SiGe is removed above the nFET regions. A device includes a silicon channel above the nFET regions and a SiGe channel above the pFET regions. | 09-30-2010 |
20120187522 | STRUCTURE AND METHOD FOR REDUCTION OF VT-W EFFECT IN HIGH-K METAL GATE DEVICES - A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices. | 07-26-2012 |
20130032897 | MOSFET GATE ELECTRODE EMPLOYING ARSENIC-DOPED SILICON-GERMANIUM ALLOY LAYER - A stack of a gate dielectric layer, a metallic material layer, an amorphous silicon-germanium alloy layer, and an amorphous silicon layer is deposited on a semiconductor substrate. In one embodiment, the amorphous silicon-germanium alloy layer is deposited as an in-situ amorphous arsenic-doped silicon-germanium alloy layer. In another embodiment, the amorphous silicon-germanium alloy layer is deposited as intrinsic semiconductor material layer, and arsenic is subsequently implanted into the amorphous silicon-germanium alloy layer. The stack is patterned and annealed to form a gate electrode. | 02-07-2013 |
20130140670 | STRUCTURE AND METHOD FOR REDUCTION OF VT-W EFFECT IN HIGH-K METAL GATE DEVICES - A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices. | 06-06-2013 |
20130256766 | SPACER AND PROCESS TO ENHANCE THE STRAIN IN THE CHANNEL WITH STRESS LINER - Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of a first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers. | 10-03-2013 |
20130334618 | METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) GATE TERMINATION - A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure. | 12-19-2013 |
20130337624 | METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) GATE TERMINATION - A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure. | 12-19-2013 |
20150064897 | PROCESS VARIABILITY TOLERANT HARD MASK FOR REPLACEMENT METAL GATE FINFET DEVICES - Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall. | 03-05-2015 |
20150287629 | Method and Structure to Reduce FET Threshold Voltage Shift Due to Oxygen Diffusion - Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials. | 10-08-2015 |
Patent application number | Description | Published |
20090164513 | Method and Apparatus For Mapping Encrypted and Decrypted Data Via Key Management System - A data processing system having a host computer including a key manager, a control unit connected to the host computer, a data storage unit (such as a tape drive) controlled by the control unit, and data storage medium for storing data thereon to be written to or read from by the data storage unit. The key manager stores a data structure having at least one record having a volume serial number, as start location, a length entry, and a key for encrypting and decrypting data on the data storage medium. A data storage medium (such as data tape) is mounted on the data storage unit, and a volume recorded on the tape is retrieved. The control unit retrieves the data structure from the key manager and matches the volume serial number recorded in the retrieved data structure with the volume serial number retrieved from the data storage medium. It they match, the control unit passes to the data storage unit, commands to turn on or turn off encryption dependent upon the location where data is written by the data storage unit onto the data storage medium, or to turn on or turn off decryption dependent upon the location where data is read by the data storage unit from the data storage medium. | 06-25-2009 |
20090185685 | TRUST SESSION MANAGEMENT IN HOST-BASED AUTHENTICATION - In a distributed, multinode data processing environment, computationally more intense public key cryptography is used to establish computationally less challenging symmetric key cryptographic paths which are thus enabled for longer term communication interchanges and in particular for establishing a client's network identity. | 07-23-2009 |
20090220089 | METHOD AND APPARATUS FOR MAPPING ENCRYPTED AND DECRYPTED DATA VIA A MULTIPLE KEY MANAGEMENT SYSTEM - A method, apparatus and program product for encryption/decryption of data on a volume of data storage media including dividing the volume into a plurality of locations, assigning a unique key to each location for encryption/decryption of data in the respective location of the volume, mapping the locations and keys in the key manager, and encrypting/decrypting data on the volume based on the data's physical location on the volume. The owning entity owning each location on the volume may also be mapped, and the keys for each location owned by the same owning entity may be the same. | 09-03-2009 |
20090245518 | SECURE COMMUNICATIONS IN COMPUTER CLUSTER SYSTEMS - A system to improve communication security in cluster machine processing may include interconnected computers that can jointly process data. The system may also include a shared secret key used by each of the interconnected computers to encrypt, decrypt, and/or authenticate data being sent, or received, from one of the interconnected computers to another of the interconnected computers. The system may further include a new shared secret key used by each of the interconnected computers to encrypt, decrypt, and/or authenticate data being sent, or received, from one of the interconnected computers to another of the interconnected computers. In addition, the new shared secret key may coexist with the shared secret key without adversely affecting the joint processing of data performed by the plurality of interconnected computers. | 10-01-2009 |
20140177455 | METHOD AND APPARATUS TO MONITOR AND ANALYZE END TO END FLOW CONTROL IN AN ETHERNET/ENHANCED ETHERNET ENVIRONMENT - A method and system for monitoring and analyzing flow control of packets in a communications network which includes multiple data transmission paths. The communications network has a first data path including an initiating node and a target node. A test frame is generated by an initiator module of a program executed by a computer for transmission over the first data path. The initiator module transmits the test frame over the first data path from the initiating node to the target node, wherein the test frame records a starting timestamp recorded by the initiating node upon transmitting the test frame. The test frame records a half trip timestamp recorded by the target node upon the test frame being received by the target node. The test frame records an end timestamp recorded by the initiating node, upon the test frame being received at the initiating node from the target node. | 06-26-2014 |
20150333866 | LINK SPEED DOWNSHIFTING FOR ERROR DETERMINATION AND PERFORMANCE ENHANCEMENTS - Various embodiments for regulating link speed for performance enhancement and port diagnosis are provided. In response to identifying an amount of errors in a communications link above a predetermined threshold, an applicable transmission speed is selectively reduced. The selective reduction occurs upon one of a temporary, permanent, and user-defined basis, and the selective reduction is performed using one of a manual setting adjustment and speed negotiation logic applied to the communications link. If errors identified at the reduced transmission speed are found to decrease, a communications port incorporating the communications link is flagged as potentially dirty, and if the errors identified at the reduced transmission speed are found to remain constant, the communications port is flagged as potentially bad. | 11-19-2015 |
Patent application number | Description | Published |
20100172575 | Method Of Detecting Red-Eye Objects In Digital Images Using Color, Structural, And Geometric Characteristics - Disclosed are methods, devices, and computer program products for red-eye detection in a digital image. In one example embodiment, a method for detecting a red-eye effect in a digital image includes several acts. First, red pixels having a predetermined degree of redness are identified in the image. Next, redness contrast is detected with respect to each of the red pixels and redness is then enhanced for those red pixels having a predetermined level of redness contrast. The pixels identified as being red are then further refined by applying another redness threshold based on one or more color characteristics associated with the red pixels. The refined set of red pixels may then be partitioned into a set of one or more candidate red-eye objects. A candidate red-eye object may be removed as a false positive based on geometric constraints associated with red-eye objects and/or proximity of the object to pixels with human skin-like color tones. | 07-08-2010 |
20100172584 | Method Of Classifying Red-Eye Objects Using Feature Extraction And Classifiers - Disclosed are methods, devices, and computer program products for red-eye detection in an image. In one example embodiment, a method for detecting red-eye objects in an image includes several acts. First, a set of candidate red-eye objects identified in the image is received. Then, features are extracted from the candidate red-eye objects and, with a plurality of classifiers, a false red-eye object is eliminated from the set of candidate red-eye objects based on the extracted features. First and second ones of the plurality of classifiers are optimized for classifying objects in a first range of sizes using first and second ones of the extracted features, respectively. Furthermore, third and fourth ones of the plurality of classifiers are also optimized for classifying objects using the first and second ones of the extracted features, respectively, but for objects in a second range of sizes. | 07-08-2010 |
Patent application number | Description | Published |
20080231480 | Distributed on-demand media transcoding system and method - A method for delivering media content over a network includes transcoding the media content to generate multiple copies of the media content, each of the multiple copies having a different destination type or a different source type or both, storing the multiple copies in a cache, receiving requests for the media content, and selecting and delivering a copy of one of the multiple copies in response to each of the requests. A further method for providing media content transcoding services includes fetching media content, selecting one of multiple transcoders for transcoding from multiple source types to multiple destination types, wherein the one transcoder is selected based at least on the destination type, sending the media content to the selected transcoder, transcoding the media content to the destination type, thereby generating transcoded media content, and transmitting the transcoded media content. | 09-25-2008 |
20110140937 | DISTRIBUTED ON-DEMAND MEDIA TRANSCODING SYSTEM AND METHOD - A method for delivering media content over a network includes transcoding the media content to generate multiple copies of the media content, each of the multiple copies having a different destination type or a different source type or both, storing the multiple copies in a cache, receiving requests for the media content, and selecting and delivering a copy of one of the multiple copies in response to each of the requests. A further method for providing media content transcoding services includes fetching media content, selecting one of multiple transcoders for transcoding from multiple source types to multiple destination types, wherein the one transcoder is selected based at least on the destination type, sending the media content to the selected transcoder, transcoding the media content to the destination type, thereby generating transcoded media content, and transmitting the transcoded media content. | 06-16-2011 |
20140019595 | DISTRIBUTED ON-DEMAND MEDIA TRANSCODING SYSTEM AND METHOD - A method for delivering media content over a network includes transcoding the media content to generate multiple copies of the media content, each of the multiple copies having a different destination type or a different source type or both, storing the multiple copies in a cache, receiving requests for the media content, and selecting and delivering a copy of one of the multiple copies in response to each of the requests. A further method for providing media content transcoding services includes fetching media content, selecting one of multiple transcoders for transcoding from multiple source types to multiple destination types, wherein the one transcoder is selected based at least on the destination type, sending the media content to the selected transcoder, transcoding the media content to the destination type, thereby generating transcoded media content, and transmitting the transcoded media content. | 01-16-2014 |
Patent application number | Description | Published |
20090201042 | THIN FILM TRANSISTOR ARRAY HAVING TEST CIRCUITRY - A thin film transistor (TFT) array having test circuitry includes a thin film transistor array body having a plurality of pixels. Test circuitry is integrally formed with the body. The test circuitry includes a power supply for supplying power via the test circuitry to the body; and a plurality of wireless switches to activate selected pixels. | 08-13-2009 |
20100164519 | TESTING OF ELECTRONIC CIRCUITS USING AN ACTIVE PROBE INTEGRATED CIRCUIT - A method and apparatus are provided for transmission/reception of signals between automatic test equipment (ATE) and a device under test (DUT). A probe card has a plurality of associated proximate active probe integrated circuits (APIC) connected to a plurality of probes. Each APIC interfaces with one or more test interface points on the DUT through probes. Each APIC receives and processes signals communicated between the ATE and the DUT. Low information content signals transmitted from the ATE are processed into high information content signals for transmission to the probe immediately adjacent the APIC, and high information content or time critical signals received by the APIC from the DUT are transmitted as low information content signals to the ATE. Because the APIC is immediately adjacent the probe there is minimum loss or distortion of the information in the signal from the DUT. | 07-01-2010 |
20110006794 | METHOD AND APPARATUS FOR INTERROGATING ELECTRONIC EQUIPMENT COMPONENTS - An apparatus for interrogating an electronic circuit supported by a substrate includes a tester external to the substrate and comprising an tester transceiver. A testing circuit is supported by the substrate and connected to the electronic circuit. The testing circuit includes a processor and a testing circuit transceiver in communication with the tester transceiver for transmitting instructions from the tester to the processor and for transmitting results of an interrogation from the processor to the tester. The processor being programmed to process instructions from the tester to interrogate the electronic circuit with an interrogation corresponding to the instructions. | 01-13-2011 |
20110057291 | ULTRA HIGH SPEED SIGNAL TRANSMISSION/RECEPTON - An interconnect for transmitting an electric signal between electronic devices includes a first coupling element electromagnetically coupled to, and immediately juxtaposed to, a second coupling element. The first coupling element is mounted on and is electrically connected to a first electronic device having a first integrated circuit. The second coupling element may be mounted on and electrically connected to the first electronic device, and electrically connected to an interconnect on a second electronic device, or the second coupling element may be mounted on and electrically connected to the second electronic device. | 03-10-2011 |
20110254123 | ULTRA HIGH SPEED SIGNAL TRANSMISSION/RECEPTION - There is provided, in combination, an integrated circuit chip, a device, and a multilayered structure mounted between the integrated circuit chip and the device. The multilayered structure has signal pathways that transfer signals between the integrated circuit chip and the device, and at least one signal pathway with a first wireless coupling element in the multilayered structure that is in communication with a second wireless coupling element in one of the integrated circuit chip, the device, and the multilayered structure. | 10-20-2011 |
20130135041 | ULTRA HIGH SPEED SIGNAL TRANSMISSION/RECEPTION - An interconnect for transmitting an electric signal between electronic devices includes a first coupling element electromagnetically coupled to, and immediately juxtaposed to, a second coupling element. The first coupling element is mounted on and is electrically connected to a first electronic device having a first integrated circuit. The second coupling element may be mounted on and electrically connected to the first electronic device, and electrically connected to an interconnect on a second electronic device, or the second coupling element may be mounted on and electrically connected to the second electronic device. | 05-30-2013 |
20130278377 | WIRELESS SENSOR DEVICE - A wireless sensor device includes a processor connected to a wireless transmitter and at least one sensor, and a power source connected to power the processor and the wireless transmitter. The processor has two or more states. An internal control element senses at least one predetermined condition. The internal control element switches the processor between states based on the occurrence of at least one predetermined condition. A molded body encloses at least the processor, the wireless transmitter, and the internal control sensor. The internal control sensor is physically isolated within the molded body. | 10-24-2013 |
20150276805 | TESTING OF ELECTRONIC CIRCUITS USING AN ACTIVE PROBE INTEGRATED CIRCUIT - A method and apparatus are provided for transmission/reception of signals between automatic test equipment (ATE) and a device under test (DUT). A probe card has a plurality of associated proximate active probe integrated circuits (APIC) connected to a plurality of probes. Each APIC interfaces with one or more test interface points on the DUT through probes. Each APIC receives and processes signals communicated between the ATE and the DUT. Low information content signals transmitted from the ATE are processed into high information content signals for transmission to the probe immediately adjacent the APIC, and high information content or time critical signals received by the APIC from the DUT are transmitted as low information content signals to the ATE. Because the APIC is immediately adjacent the probe there is minimum loss or distortion of the information in the signal from the DUT. | 10-01-2015 |