| Patent application number | Description | Published |
|---|
| 20090055675 | Adjustable Byte Lane Offset For Memory Module To Reduce Skew - Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte lane with otherwise would arrive early to their destinations. Such on-chip delay is provided delay circuits preferably positioned directly before the output buffers/bond pads of the integrated circuit or module. By intentionally delaying some of the outputs from the integrated circuit or module, external skew is compensated for so that all data in the byte lane arrives at the destination at substantially the same time. In a preferred embodiment, the delay circuits are programmable to allow the integrated circuit or module to be freely tailored to environments having different skew considerations, such as different styles of connectors. | 02-26-2009 |
| 20090067267 | MEMORY DEVICE AND METHOD HAVING LOW-POWER, HIGH WRITE LATENCY MODE AND HIGH-POWER, LOW WRITE LATENCY MODE AND/OR INDEPENDENTLY SELECTABLE WRITE LATENCY - A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active. | 03-12-2009 |
| 20090276548 | DYNAMICALLY SETTING BURST TYPE OF A DOUBLE DATA RATE MEMORY DEVICE - One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device. | 11-05-2009 |
| 20090307446 | DYNAMICALLY SETTING BURST LENGTH OF A DOUBLE DATA RATE MEMORY DEVICE - One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device. | 12-10-2009 |
| 20100097878 | USER SELECTABLE BANKS FOR DRAM - A memory device includes a configurable array of memory cells. A number of array banks is configured based upon data stored in a mode register or decoded by logic circuitry. The memory device remains a full capacity memory, regardless of the number of array banks. Memory address decoding circuitry is adjusted to route address signals to or from a bank address decoder based upon the number of array banks selected. | 04-22-2010 |
| 20100262872 | METHOD AND APPARATUS FOR DETECTING COMMUNICATION ERRORS ON A BUS - A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The invention may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory. | 10-14-2010 |
| 20100332718 | SYSTEM AND METHOD FOR PROVIDING CONFIGURABLE LATENCY AND/OR DENSITY IN MEMORY DEVICES - Memory devices, memory controllers, methods, and systems are provided, such as methods for masking the row cycle latency time of a memory array. In one embodiment, a memory device that is configurable to operate in full or reduced density modes is provided. In a reduced density mode, certain banks within the memory array function as duplicate memory banks associated with an addressable memory bank. Write operations performed in the reduced density mode may write a data segment to an addressed memory bank as well as its associated duplicate banks. When repeated read requests are issued for the data segment, the read requests may be interleaved between the addressed bank and its duplicate banks, thereby masking the row cycle time of each physical bank. That is, the interval between each read out of the data segment from the memory array will appear to be less than the row cycle time. | 12-30-2010 |
| 20110038217 | MEMORY DEVICE AND METHOD HAVING LOW-POWER, HIGH WRITE LATENCY MODE AND HIGH-POWER, LOW WRITE LATENCY MODE AND/OR INDEPENDENTLY SELECTABLE WRITE LATENCY - A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active. | 02-17-2011 |
