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Christopher P. Ausschnitt

Christopher P. Ausschnitt, Lexington, MA US

Patent application number	Description	Published
20080259334	MULTI LAYER ALIGNMENT AND OVERLAY TARGET AND MEASUREMENT METHOD - A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.	10-23-2008
20090011346	FOCUS BLUR MEASUREMENT AND CONTROL METHOD - A method for optimizing imaging and process parameter settings in a lithographic pattern imaging and processing system. The method includes correlating the dimensions of a first set of at least one control pattern printed in a lithographic resist layer, measured at three or more locations on or within the pattern which correspond to differing dose, defocus and blur sensitivity. The method then includes measuring the dimensions on subsequent sets of control patterns, printed in a lithographic resist layer, at three or more locations on or within each pattern, of which a minimum of three locations match those measured in the first set, and determining the effective dose, defocus and blur values associated with forming the subsequent sets of control patterns by comparing the dimensions at the matching locations with the correlated dependencies.	01-08-2009
20090053627	METHODS AND SYSTEMS FOR NORMALIZING ERROR - A method for fabricating parts using a photolithography system, includes: performing a search of normalization data for an estimated dose operating point; and using the estimated dose operating point for fabrication of new parts. Other methods are provided.	02-26-2009
20110058170	MULTI LAYER ALIGNMENT AND OVERLAY TARGET AND MEASUREMENT METHOD - A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.	03-10-2011
20110069314	MULTILAYER ALIGNMENT AND OVERLAY TARGET AND MEASUREMENT METHOD - A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.	03-24-2011

Christopher P. Ausschnitt, Boston, MA US

Patent application number	Description	Published
20090186286	Method To Control Semiconductor Device Overlay Using Post Etch Image Metrology - A method of determining positioning error between lithographically produced integrated circuit patterns on at least two different lithographic levels of a semiconductor wafer comprising. The method includes exposing, developing and etching one or more lithographic levels to create one or more groups of marks comprising a target at one or more wafer locations. The method then includes exposing and developing a subsequent group of marks within the target on a subsequent lithographic level. The method then comprises measuring the position of the marks on each level with respect to a common reference point, and using the measured positions of the groups of marks to determine the relative positioning error between one or more pairs of the developed and etched lithographic levels on which the marks are located.	07-23-2009
20100190096	TARGET AND METHOD FOR MASK-TO-WAFER CD, PATTERN PLACEMENT AND OVERLAY MEASUREMENT AND CONTROL - A method for mask-to-wafer correlation among multiple masking levels of a semiconductor manufacturing process. The method includes creating compact targets containing structure patterns suitable for pattern placement, critical dimension and overlay measurement at a set of common locations on two or more patterning layers, and creating at least two masks containing functional circuit structure patterns and the compact targets at locations between functional circuit structure patterns. The method then includes measuring the targets, determining overlay variation between the masks, exposing and creating with one mask a first lithographic processing layer on a wafer, and exposing and creating with another mask a second lithographic processing layer on the wafer, over the first layer. The method further includes measuring the targets on the wafer at one or more of the layers, and correlating the mask and wafer measurements to distinguish mask and lithography induced components of critical dimension and overlay variation.	07-29-2010

Christopher P. Ausschnitt, Waltham, MA US

Patent application number	Description	Published
20090011342	METHOD TO OPTIMIZE GRATING TEST PATTERN FOR LITHOGRAPHY MONITORING AND CONTROL - A method of making a process monitor grating pattern for use in a lithographic imaging system comprises determining minimum resolvable pitch of a plurality of spaced, adjacent line elements, and selecting a process monitor grating period that is an integer multiple M, greater than 1, of the minimum resolvable pitch. The method then includes designing a process monitor grating pattern having a plurality of adjacent sets of grouped line elements spaced from each other. Each set of grouped line elements is spaced from and parallel to an adjacent set of grouped line elements by the process monitor grating period, such that when the process monitor grating pattern is projected by the lithographic imaging system the line elements in each set are unresolvable from each other and Fourier coefficients of diffracted orders m created by the line elements in the range of 1<|m|≦M are zero.	01-08-2009

Christopher P. Ausschnitt, Boca Raton, FL US

Patent application number	Description	Published
20110248388	MULTI-LAYER CHIP OVERLAY TARGET AND MEASUREMENT - A wafer includes an active region and a kerf region surrounding at least a portion of the active region. The wafer also includes a target region having a rectangular shape with a width and a length greater than the width, the target region including one or more target patterns, at least one of the target patterns being formed by two sub-patterns disposed at opposing corners of a target rectangle disposable within the target region.	10-13-2011