Patent application number | Description | Published |
20120059971 | METHOD AND APPARATUS FOR HANDLING CRITICAL BLOCKING OF STORE-TO-LOAD FORWARDING - The present invention provides a method and apparatus for handling critical blocking of store-to-load forwarding. One embodiment of the method includes recording a load that matches an address of a store in a store queue before the store has valid data. The load is blocked because the store does not have valid data. The method also includes replaying the load in response to the store receiving valid data so that the valid data is forwarded from the store queue to the load. | 03-08-2012 |
20120110280 | OUT-OF-ORDER LOAD/STORE QUEUE STRUCTURE - The present invention provides a method and apparatus for supporting embodiments of an out-of-order load/store queue structure. One embodiment of the apparatus includes a first queue for storing memory operations adapted to be executed out-of-order with respect to other memory operations. The apparatus also includes one or more additional queues for storing memory operation in response to completion of a memory operation. The embodiment of the apparatus is configured to remove the memory operation from the first queue in response to the completion. | 05-03-2012 |
20120110304 | PIPELINED SERIAL RING BUS - The present invention provides embodiments of an apparatus used to implement a pipelined serial ring bus. One embodiment of the apparatus includes one or more ring buses configured to communicatively couple registers associated with logical elements in a processor. The ring bus(s) are configured to concurrently convey information associated with a plurality of load or store operations. | 05-03-2012 |
20120117335 | LOAD ORDERING QUEUE - A method and apparatus to utilize a strong ordering scheme to be performed on memory operations in a processor to prevent performance degradation caused by out-of-order memory operations is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes storing information associated with a first load operation in a load queue, the first load operation being executed out-of-order with respect to one or more second load operations. The method also includes detecting a snoop hit on the first load operation. The method further includes re-executing the first load operation in response to detecting the snoop hit. | 05-10-2012 |
20120124296 | METHOD AND APPARATUS FOR REACQUIRING LINES IN A CACHE - A method and apparatus for controlling re-acquiring lines of memory in a cache is provided. The method comprises storing at least one atomic instruction in a queue in response to the atomic instruction being retired, and identifying a target memory location associated with load and store portions of the atomic instruction. A line of memory associated with the target memory location is acquired and stored in a cache. Subsequently, if the line of acquired memory is evicted, then it is re-acquired in response to the atomic instruction becoming the oldest instruction stored in the queue. The apparatus comprises a queue and a cache. The queue is adapted for storing at least one atomic instruction in response to the atomic instruction being retired. A target memory location is associated with load and store portions of the atomic instruction. The cache is adapted for acquiring a line of memory associated with the target memory location, storing the line of acquired memory in a cache, evicting the acquired line of memory from the cache in response to detecting a conflict regarding the acquired line of memory, and re-acquiring the line of memory in response to the atomic instruction becoming the oldest instruction stored in the queue. | 05-17-2012 |
20120124325 | METHOD AND APPARATUS FOR CONTROLLING A TRANSLATION LOOKASIDE BUFFER - A method and apparatus are provided for controlling a translation lookaside buffer in connection with the execution of an atomic instruction. The method comprises identifying load instructions within a plurality of instructions to be executed, and placing the identified load instructions in a queue prior to execution. An atomic instruction identified in the queue is prevented from executing until the atomic instruction is the oldest instruction in the queue. The apparatus comprises a queue and a translation lookaside buffer. The queue is adapted to: identify an atomic instruction within a plurality of instructions to be executed; prevent execution of the atomic instruction until it is the oldest instruction in the queue; and send a virtual address corresponding to the atomic instruction and an atomic load signal in response to determining that the atomic instruction is the oldest instruction in the queue. The translation lookaside buffer is adapted for maintaining at least one virtual to physical address translation, and is adapted to force a miss in the translation lookaside buffer in response to receiving the atomic load signal. | 05-17-2012 |
20120124586 | SCHEDULING SCHEME FOR LOAD/STORE OPERATIONS - A method and apparatus are provided to control the order of execution of load and store operations. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create the apparatus. One embodiment of the method includes determining whether a first group, comprising at least one or more instructions, is to be selected from a scheduling queue of a processor for execution using either a first execution mode or a second execution mode. The method also includes, responsive to determining that the first group is to be selected for execution using the second execution mode, preventing selection of the first group until a second group, comprising at least one or more instructions, that entered the scheduling queue prior to the first group is selected for execution. | 05-17-2012 |
20130031332 | MULTI-CORE SHARED PAGE MISS HANDLER - Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system. One embodiment of such a method comprises receiving one or more page miss requests from one or more respective requesting devices of the plurality of devices in the multi-core system, and arbitrating to identify a first page miss requests of the one or more requesting devices A page table walk is performed to generate a physical address responsive to the first page miss request. Then the physical address is sent to the corresponding requesting device, or a fault is signaled to an operating system for the corresponding requesting device responsive to the first page miss request. | 01-31-2013 |