| Patent application number | Description | Published |
|---|
| 20080278207 | FALL TIME ACCELERATOR CIRCUIT - Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time. Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus. | 11-13-2008 |
| 20090019211 | Establishing A Redundant Array Of Inexpensive Drives - Establishing, with a USB RAID controller connected to a USB hub and with USB mass storage devices connected to the USB hub and the USB RAID controller through USB connectors, the USB hub controlled by a USB host controller, a RAID array including enumerating, by the USB host controller, the USB mass storage devices, including discovering the USB RAID controller; receiving, by the USB RAID controller from a RAID console application program, an instruction to designate USB connectors as RAIDable USB connectors, the instruction including selected USB connectors; designating, by the USB RAID controller, the selected USB connectors as RAIDable USB connectors; enumerating by the USB RAID controller the USB mass storage devices connected to the RAIDable USB connectors; configuring by the USB RAID controller a RAID array, the RAID array including the USB mass storage devices; and storing, through the USB RAID controller, computer data on the RAID array. | 01-15-2009 |
| 20090083472 | DESIGN STRUCTURE FOR A MEMORY SWITCHING DATA PROCESSING SYSTEM - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory switching data processing system is provided. The memory switching data processing system includes one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules. | 03-26-2009 |
| 20090083529 | Memory Switching Data Processing System - A memory switching data processing system including one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules. | 03-26-2009 |
| 20090133010 | VIRTUALIZED BLADE FLASH WITH MANAGEMENT MODULE - The invention is directed to providing a virtualized blade flash with a management module in a blade server. A method of configuring a blade server according to an embodiment of the invention includes: providing a plurality of blades, wherein each blade comprising: a service processor; a chip set; an at least one central processing unit (CPU); providing a management module in communication with each of the plurality of blades; and adding a virtual flash store at the management module. | 05-21-2009 |
| 20090219835 | Optimizing A Physical Data Communications Topology Between A Plurality Of Computing Nodes - Methods, apparatus, and products are disclosed for optimizing a physical data communications topology between a plurality of computing nodes, the physical data communications topology including physical links configured to connect the plurality of nodes for data communications, that include carrying out repeatedly at a predetermined pace: detecting network packets transmitted through the links between each pair of nodes in the physical data communications topology, each network packet characterized by one or more packet attributes; assigning, to each network packet, a packet weight in dependence upon the packet attributes for that network packet; determining, for each pair of nodes in the physical data communications topology, a node pair traffic weight in dependence upon the packet weights assigned to the network packets transferred between that pair of nodes; and reconfiguring the physical links between each pair of nodes in dependence upon the node pair traffic weights. | 09-03-2009 |
| 20090281761 | Detecting An Increase In Thermal Resistance Of A Heat Sink In A Computer System - Methods, apparatus, and products for detecting an increase in thermal resistance of a heat sink in a computer system, the heat sink dissipating heat for a component of the computer system, the computer system including a fan controlling airflow across the heat sink, the computer system also including a temperature monitoring device, including: measuring, by a monitoring module through use of the temperature monitoring device during operation of the computer system, thermal resistance of the heat sink; determining whether the measured thermal resistance of the heat sink is greater than a threshold thermal resistance, the threshold thermal resistance stored in a thermal profile in non-volatile memory, and if the measured thermal resistance of the heat sink is greater than the threshold thermal resistance, notifying a system administrator. | 11-12-2009 |
| 20110138044 | WAKE ON LOCAL AREA NETWORK SIGNALLING IN A MULTI-ROOT I/O VIRTUALIZATION - Wake on local area network (LAN) functionality is provided in a multi-root environment. An I/O device, which is share by a plurality of physical hosts, receives the MAC address contained in the wake up packet, then prepares and sends an appropriate wake signal to the targeted host. In one embodiment, the shared I/O device sends an out-of-band wake up signal to each of the physical host computers, wherein the wake up signal is a serial bit stream encoded with the MAC address so that only the physical host having a MAC address matching the MAC address in the wake up signal will be turned on. In another embodiment, the shared I/O device sends a binary ON/OFF signal directly to the targeted physical host computer over a signal line associated with the MAC address. | 06-09-2011 |
