| Patent application number | Description | Published |
|---|
| 20080246086 | SEMICONDUCTOR DEVICES HAVING CHARGE BALANCED STRUCTURE - A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region. | 10-09-2008 |
| 20090111231 | Method for Forming Shielded Gate Field Effect Transistor Using Spacers - A trench is formed in a semiconductor region. A dielectric layer lining sidewalls and bottom surface of the trench is formed. The dielectric layer is thicker along lower sidewalls and the bottom surface than along upper sidewalls of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. Dielectric spacers are formed along the upper trench sidewalls. After forming the dielectric spacers, an inter-electrode dielectric (IED) is formed in the trench over the shield electrode. After forming the IED, the dielectric spacers are removed. | 04-30-2009 |
| 20100006927 | Charge Balance Techniques for Power Devices - A vertically-conducting charge balance semiconductor power device includes an active area comprising a plurality of cells capable of conducting current along a vertical dimension when biased in a conducting state, and a non-active perimeter region surrounding the active area. No current flows along the vertical dimension through the non-active perimeter region when the plurality of cells is biased in the conducting state. Strips of p pillars and strips of n pillars are arranged in an alternating manner. The strips of p pillars have a depth extending along the vertical dimension, a width, and a length. The strips of p and n pillars extend through both the active area and the non-active perimeter region along a length of a die that contains the semiconductor power device. The length of the die extends parallel to the length of the strips of p pillars. Each of the strips of p pillars includes a plurality of discontinuities forming portions of a plurality of strips of n regions. The plurality of strips of n regions extends in the non-active perimeter region perpendicular to the length of the die. | 01-14-2010 |
| 20100315159 | HIGH VOLTAGE POWER INTEGRATED CIRCUIT - A high performance, power integrated circuit composed of two charge balanced, extended drain NMOS transistors (CBDEMOS) formed on an n-substrate. A CBDENMOS transistor with an n-type substrate source. A charge balanced channel diode (CBCD) with an n-type substrate. A process for forming a high performance, power integrated circuit composed of two CBDENMOS transistors formed on an n-substrate. A process for forming a power integrated circuit composed of one CBDENMOS transistor and one CBCD on an n-type substrate. | 12-16-2010 |
| 20110212586 | Method for Forming Shielded Gate Field Effect Transistors - A method for forming a field effect transistor includes forming a trench in a semiconductor region and forming a dielectric layer lining lower sidewalls and bottom surface of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. An inter-electrode dielectric (IED) is formed in the trench over the shield electrode by carrying out a steam ambient oxidation and carrying out a dry ambient oxidation. A gate electrode is formed in an upper portion of the trench. The gate electrode may be insulated from the shield electrode by the IED. | 09-01-2011 |
| 20110241172 | Charge Balance Techniques for Power Devices - A silicon wafer includes a silicon region of first conductivity type and a plurality of strips of second conductivity type pillars extending in parallel in the silicon region from a location along a perimeter of the silicon wafer to an opposing location along the perimeter of the silicon wafer. The plurality of strips of second conductivity type pillars extend to a predetermined depth within the silicon region. | 10-06-2011 |
| 20110303976 | HIGH VOLTAGE CHANNEL DIODE - A channel diode structure having a drift region and method of forming. A charge balanced channel diode structure having an electrode shield and method of forming. | 12-15-2011 |
