| Patent application number | Description | Published |
|---|
| 20090067213 | Method of forming controllably conductive oxide - In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is then formed on the layer. | 03-12-2009 |
| 20090109598 | Metal-insulator-metal (MIM) device and method of formation thereof - In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening. | 04-30-2009 |
| 20090109727 | Erase, programming and leakage characteristics of a resistive memory device - The present method provides annealing of a resistive memory device so as to provide that the device in its erased state has a greatly increased resistance as compared to a prior art approach. The annealing also provides that the device may be erased by application of any of a plurality of electrical potentials within an increased range of electrical potentials as compared to the prior art. | 04-30-2009 |
| 20100208517 | PIN DIODE DEVICE AND ARCHITECTURE - A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line. | 08-19-2010 |
