| Patent application number | Description | Published |
|---|
| 20080211568 | MuGFET POWER SWITCH - A multi-gate field effect transistor power switch is used to selectively couple a circuit to a supply voltage. In various embodiments, both n and p-type multi-gate field effect transistor power switches may be used to couple sub-circuits of varying granularity to different voltage supplies. | 09-04-2008 |
| 20080224178 | RESISTIVE MEMORY AND METHOD - A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area. | 09-18-2008 |
| 20080283925 | Multi-Fin Component Arrangement and Method for Manufacturing a Multi-Fin Component Arrangement - In a first embodiment, a multi-fin component arrangement has a plurality of multi-fin component partial arrangements. Each of the multi-fin component partial arrangements has a plurality of electronic components, which electronic components have a multi-fin structure. At least one multi-fin component partial arrangement has at least one dummy structure, which at least one dummy structure is formed between at least two of the electronic components formed in the at least one multi-fin component partial arrangement. The dummy structure is formed in such a way that electrical characteristics of the electronic components formed in the multi-fin component partial arrangements are adapted to one another. | 11-20-2008 |
| 20090101975 | Integrated Circuit Arrangement Comprising a Field Effect Transistor, Especially a Tunnel Field Effect Transistor - An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD | 04-23-2009 |
| 20100194400 | Circuit Arrangement With A Test Circuit And A Reference Circuit And Corresponding Method - Implementations are presented herein that include a test circuit and a reference circuit. | 08-05-2010 |
| 20110013668 | SEMICONDUCTOR CIRCUIT ARRANGEMENT AND ASSOCIATED METHOD FOR TEMPERATURE DETECTION - A semiconductor circuit arrangement and a method for temperature detection is disclosed. One embodiment includes a semiconductor substrate, on which is formed a first insulating layer and thereon a thin active semiconductor region, which is laterally delimited by a second insulating layer. In the active semiconductor region, a first and second doping zone are formed on the surface of the first insulating layer for the definition of a channel zone, wherein there is formed at the surface of the channel zone a gate dielectric and thereon a control electrode for the realization of a field effect transistor. In the active semiconductor region, a diode doping zone is formed on the surface of the first insulating layer, which zone realizes a measuring diode via a diode side area with the first or second doping zone and is delimited by the second insulating layer at its further side areas. | 01-20-2011 |
| 20110095347 | VERTICAL DIODE USING SILICON FORMED BY SELECTIVE EPITAXIAL GROWTH - Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus. | 04-28-2011 |
| 20120026781 | RESISTIVE MEMORY AND METHOD - A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area. | 02-02-2012 |
