| Patent application number | Description | Published |
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| 20110001169 | FORMING UNIFORM SILICIDE ON 3D STRUCTURES - By using a non-conformal diffusion barrier in conjunction with a similarly deposited non-conformal initial deposition of siliciding material, a substantially uniform and conformal silicide can be formed in a 3D structure such as the fin of a FinFET. The siliciding material may be nickel (Ni), the diffusion barrier may be titanium (Ti) or titanium nitride (TiN). Generally, the diffusion barrier may be any material which will inhibit, but not block, diffusion of the siliciding material into the silicon. In this manner, a non-conformal barrier deposition, in conjunction with a non-conformal silicide material deposition, after anneal, results in substantially conformal silicide formation. | 01-06-2011 |
| 20110080180 | VARYING CAPACITANCE VOLTAGE CONTRAST STRUCTURES TO DETERMINE DEFECT RESISTANCE - A method for determining resistances of defects in a test structure, comprising: forming a first layer of the test structure having elements under test; generating a first e-beam image of the first layer, the first e-beam image graphically identifying defects detected at the first layer, each defect at the first layer having a corresponding grey scale level; adding capacitance to the structure by forming a metal layer of the structure; generating a second e-beam image of the metal layer, the second e-beam image graphically identifying defects detected at the metal layer, each defect at the metal layer having a corresponding grey scale level; generating a pattern of grey scale levels for each defect based on the corresponding grey scale level of each defect at each layer of the test structure; and determining a resistive range of each defect based on the pattern of grey scale levels generated for each defect. | 04-07-2011 |
| 20110101472 | STRUCTURE AND METHOD TO FORM A THERMALLY STABLE SILICIDE IN NARROW DIMENSION GATE STACKS - An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a silicide region comprising Pt segregated in a region of the silicide away from the top surface of the silicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the silicide. The silicide is first formed by a formation anneal, at a temperature in the range 250° C. to 450° C. Subsequently, a segregation anneal at a temperature in the range 450° C. to 550° C. The distribution of the Pt along the vertical length of the silicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the silicide layer and the pulldown spacer height. | 05-05-2011 |
| 20110127493 | SELF ALIGNED CARBIDE SOURCE/DRAIN FET - A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure. | 06-02-2011 |
| Patent application number | Description | Published |
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| 20090026623 | BURIED METAL-SEMICONDUCTOR ALLOY LAYERS AND STRUCTURES AND METHODS FOR FABRICATION THEREOF - A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region. | 01-29-2009 |
| 20090152590 | METHOD AND STRUCTURE FOR SEMICONDUCTOR DEVICES WITH SILICON-GERMANIUM DEPOSITS - A method of forming a semiconductor device including forming a second deposit of silicon-germanium on a first deposit of silicon-germanium, the first deposit formed in a conduction terminal region of a substrate of the semiconductor device and having a first percentage of germanium, and the second deposit having a second percentage of germanium that is less than the first percentage and supports forming a silicide deposit on the second deposit. A structure is also provided. | 06-18-2009 |
| 20090315182 | SILICIDE INTERCONNECT STRUCTURE - A method for forming an interconnect structure includes forming a dielectric layer above a first layer having a conductive region defined therein. An opening is defined in the dielectric layer to expose at least a portion of the conductive region. A metal silicide is formed in the opening to define the interconnect structure. A semiconductor device includes a first layer having a conductive region defined therein, a dielectric layer formed above the first layer, and a metal silicide interconnect structure extending through the dielectric layer to communicate with the conductive region. | 12-24-2009 |
| 20100062597 | Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers - An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. | 03-11-2010 |
| 20110147809 | FORMING A CARBON CONTAINING LAYER TO FACILITATE SILICIDE STABILITY IN A SILICON GERMANIUM MATERIAL - A method includes forming a silicon germanium layer, forming a layer comprising carbon and silicon on a top surface of the silicon germanium layer, forming a metal layer above the layer comprising carbon and silicon, and performing a thermal treatment to convert at least the layer comprising carbon and silicon to form a metal silicide layer. | 06-23-2011 |
