Patent application number | Description | Published |
20090171647 | INTERCONNECT ARCHITECTURAL STATE COVERAGE MEASUREMENT METHODOLOGY - A method and apparatus for ensuring efficient validation coverage of an architecture, such as protocol or interconnect architecture, is herein described. A coverage space of states for an architecture is generated and stored in a database. During simulation, states of the coverage space encountered are marked. From this, the states encountered and not encountered may be determined. Based on the states not encountered, a targeted test suite is developed to target at least some of the states not encountered during previous simulation. This feedback loop from simulation to refining of a test suite based on states of a coverage space not encountered during simulation may be recursively repeated until adequate validation, i.e. an adequate confidence level of validation, of the coverage space is achieved. | 07-02-2009 |
20090254712 | ADAPTIVE CACHE ORGANIZATION FOR CHIP MULTIPROCESSORS - A method, chip multiprocessor tile, and a chip multiprocessor with amorphous caching are disclosed. An initial processing core | 10-08-2009 |
20100005245 | SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL WRITES AND NON-SNOOP ACCESSES - A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, when a conflict associated with a partial memory access, such as a partial write, is detected, a write-back phase is inserted at the conflict phase to write-back the partial data to a home agent. Examples messages to initiate a write-back phase at a conflict phase include: an Acknowledge Conflict Write-back message to acknowledge a conflict and provide a write-back marker at the beginning of the conflict phase, a write-back marker message before the conflict phase, a write-back marker message within the conflict phase, a write-back marker message after the conflict phase, and a postable message after the conflict phase. | 01-07-2010 |
20100005246 | SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND NON-SNOOP ACCESSES - A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data. | 01-07-2010 |
20100074106 | SCHEME FOR AVOIDING DEADLOCK IN MULTI-RING INTERCONNECT, WITH ADDITIONAL APPLICATION TO CONGESTION CONTROL - A method and system to avoid multi-ring deadlock. The method includes removing a message on a multi-ring interconnect either with a ring connector associated with the target of the message or by the message's source station such that the message travels no more than one time around the slotted ring interconnect before its removal. The method may also be applied to single ring networks for congestion control. | 03-25-2010 |
20100250861 | FAIRNESS MECHANISM FOR STARVATION PREVENTION IN DIRECTORY-BASED CACHE COHERENCE PROTOCOLS - Methods and apparatus relating to a fairness mechanism for starvation prevention in directory-based cache coherence protocols are described. In one embodiment, negatively-acknowledged (nack'ed) requests from a home agent may be tracked (e.g., using distributed linked-lists). In turn, the tracked requests may be served in a fair order. Other embodiments are also disclosed. | 09-30-2010 |
20120317369 | SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND NON-SNOOP ACCESSES - A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data. | 12-13-2012 |
20140112145 | SCHEME FOR AVOIDING DEADLOCK IN MULTI-RING INTERCONNECT, WITH ADDITIONAL APPLICATION TO CONGESTION CONTROL - A method and system to avoid multi-ring deadlock. The method includes removing a message on a multi-ring interconnect either with a ring connector associated with the target of the message or by the message's source station such that the message travels no more than one time around the slotted ring interconnect before its removal. The method may also be applied to single ring networks for congestion control. | 04-24-2014 |
20140115275 | SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND NON-SNOOP ACCESSES - A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data. | 04-24-2014 |
Patent application number | Description | Published |
20080286334 | OCULAR IMPLANT MADE BY A DOUBLE EXTRUSION PROCESS - The invention provides biodegradable implants sized for implantation in an ocular region and methods for treating medical conditions of the eye. The implants are formed from a mixture of hydrophilic end and hydrophobic end PLGA, and deliver active agents into an ocular region without a high burst release. | 11-20-2008 |
20080286336 | OCULAR IMPLANT MADE BY A DOUBLE EXTRUSION PROCESS - The invention provides biodegradable implants sized for implantation in an ocular region and methods for treating medical conditions of the eye. The implants are formed from a mixture of hydrophilic end and hydrophobic end PLGA, and deliver active agents into an ocular region without a high burst release. | 11-20-2008 |
20110305743 | OCULAR IMPLANT MADE BY A DOUBLE EXTRUSION PROCESS - The invention provides biodegradable implants sized for implantation in an ocular region and methods for treating medical conditions of the eye. The implants are formed from a mixture of hydrophilic end and hydrophobic end PLGA, and deliver active agents into an ocular region without a high burst release. | 12-15-2011 |
20110309546 | OCULAR IMPLANT MADE BY A DOUBLE EXTRUSION PROCESS - The invention provides biodegradable implants sized for implantation in an ocular region and methods for treating medical conditions of the eye. The implants are formed from a mixture of hydrophilic end and hydrophobic end PLGA, and deliver active agents into an ocular region without a high burst release. | 12-22-2011 |
20130231318 | OCULAR IMPLANT MADE BY A DOUBLE EXTRUSION PROCESS - The invention provides biodegradable implants sized for implantation in an ocular region and methods for treating medical conditions of the eye. The implants are formed from a mixture of hydrophilic end and hydrophobic end PLGA, and deliver active agents into an ocular region without a high burst release. | 09-05-2013 |
20130295157 | OCULAR IMPLANT MADE BY A DOUBLE EXTRUSION PROCES - The invention provides biodegradable implants sized for implantation in an ocular region and methods for treating medical conditions of the eye. The implants are formed from a mixture of hydrophilic end and hydrophobic end PLGA, and deliver active agents into an ocular region without a high burst release. | 11-07-2013 |
Patent application number | Description | Published |
20090049222 | PCI Express-Compatible Controller And Interface For Flash Memory - A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation. | 02-19-2009 |
20100049878 | Differential Data Transfer For Flash Memory Card - A flash memory card includes a differential datapath that enables communications between the flash memory card and a host device to be performed using differential signals. The differential datapath can translate between the differential signals and card-specific signals that control read/write operations to the memory array of the flash memory card. The card-specific signals can be standard MultimediaCard, Secure-Digital card, Memory Stick, or CompactFlash card signals, among others. A host device that provides differential data transfer capability can include a similar differential datapath. By using differential data transfer rather than conventional clocked data transfer, overall data bandwidth between a flash memory card and a host device can be significantly increased, while simultaneously decreasing power consumption and pin requirements. | 02-25-2010 |