Chou, NY
Anthony Chou, Hopewell Junction, NY US
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20110284932 | BODY CONTACT STRUCTURES AND METHODS OF MANUFACTURING THE SAME - A body contact structure which reduce parasitic capacitance and improves body resistance of a device and methods of manufacture. The method includes forming a gate insulator material and gate electrode material on a substrate. The method further includes patterning the gate insulator material and the gate electrode material to form a gate structure having a shape with a first portion isolated from a second portion. The method further includes forming source and drain regions on sides of the first portion and a body contact at a side and under an area of the second portion, and forming an interlevel dielectric within a space that isolates the first portion from the second portion of the gate structure, and over the gate structure, source and drain regions and the body contact. | 11-24-2011 |
Anthony I. Chou, Hopewell Junction, NY US
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20110163383 | BULK SUBSTRATE FET INTEGRATED ON CMOS SOI - An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET. | 07-07-2011 |
20110169064 | READ TRANSISTOR FOR SINGLE POLY NON-VOLATILE MEMORY USING BODY CONTACTED SOI DEVICE - A read transistor for single poly non-volatile memory using a body contacted SOI transistor and a method of manufacturing the same is provided. The non-volatile random access memory is formed in silicon on insulator (SOI). The non-volatile random access memory includes a read field effect transistor (FET) having a body contact formed in the silicon of the SOI. The body contact is in electrical contact with a diffusion region under a gate of the read FET. | 07-14-2011 |
20120187492 | BULK SUBSTRATE FET INTEGRATED ON CMOS SOI - An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET. | 07-26-2012 |
20130264679 | PLANAR POLYSILICON REGIONS FOR PRECISION RESISTORS AND ELECTRICAL FUSES AND METHOD OF FABRICATION - A semiconductor structure providing a precision resistive element and method of fabrication is disclosed. Polysilicon is embedded in a silicon substrate. The polysilicon may be doped to control the resistance. Embodiments may include resistors, eFuses, and silicon-on-insulator structures. Some embodiments may include non-rectangular cross sections. | 10-10-2013 |
Anthony I. Chou, Hopewell Jct., NY US
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20100237421 | Gated Diode Structure and Method Including Relaxed Liner - A gated diode structure and a method for fabricating the gated diode structure use a relaxed liner that is derived from a stressed liner that is typically used within the context of a field effect transistor formed simultaneously with the gated diode structure. The relaxed liner is formed incident to treatment, such as ion implantation treatment, of the stressed liner. The relaxed liner provides improved gated diode ideality in comparison with the stressed liner, absent any gated diode damage that may occur incident to stripping the stressed liner from the gated diode structure while using a reactive ion etch method. | 09-23-2010 |
Anthony I-Chih Chou, Beacon, NY US
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20130087787 | ELECTRICAL MASK INSPECTION - An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and the other two layers are test layers. A resistance measurement of the scan chain is used to determine if a potential defect exists within one of the vias or metal segments comprising the scan chain. | 04-11-2013 |
20140117409 | METHOD AND STRUCTURE FOR BODY CONTACTED FET WITH REDUCED BODY RESISTANCE AND SOURCE TO DRAIN CONTACT LEAKAGE - A semiconductor device and method of making same. The device includes a substrate comprising a semiconductor layer on an insulating layer, the semiconductor layer including a semiconductor body having a body contact region and an abutting switching region; a bridged gate over the semiconductor body, the bridged gate having a bridge gate portion and an abutting gate portion, the bridge gate portion comprising a multilayer first gate stack and the gate portion comprising a multilayer second gate stack comprising the gate dielectric layer on the semiconductor body; first and second source/drains formed in the switching region on opposite sides of the channel; and wherein a first work function difference between the bridge portion and the body contact region is different from a second work function difference between the gate portion and the channel region. | 05-01-2014 |
20140252539 | PLANAR POLYSILICON REGIONS FOR PRECISION RESISTORS AND ELECTRICAL FUSES AND METHOD OF FABRICATION - A semiconductor structure providing a precision resistive element and method of fabrication is disclosed. Polysilicon is embedded in a silicon substrate. The polysilicon may be doped to control the resistance. Embodiments may include resistors, eFuses, and silicon-on-insulator structures. Some embodiments may include non-rectangular cross sections. | 09-11-2014 |
20150084132 | Silicon Nitride Layer Deposited at Low Temperature to Prevent Gate Dielectric Regrowth High-K Metal Gate Field Effect Transistors - Standard High-K metal gate (HKMG) CMOS technologies fabricated using the replacement metal gate (RMG), also known as gate-last, integration flow, are susceptible to oxygen ingress into the high-K gate dielectric layer and oxygen diffusion into the gate dielectric and semiconductor channel region. The oxygen at the gate dielectric and semiconductor channel interface induces unwanted oxide regrowth that results in an effective oxide thickness increase, and transistor threshold voltage shifts, both of which are highly variable and degrade semiconductor chip performance. By introducing silicon nitride deposited at low temperature, after the metal gate formation, the oxygen ingress and gate dielectric regrowth can be avoided, and a high semiconductor chip performance is maintained. | 03-26-2015 |
Anthony I-Chih Chou, Hopewell Junction, NY US
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20120068174 | ELECTRICAL MASK INSPECTION - An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and the other two layers are test layers. A resistance measurement of the scan chain is used to determine if a potential defect exists within one of the vias or metal segments comprising the scan chain. | 03-22-2012 |
Cheng-Lung Chou, Great Neck, NY US
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20090189542 | DIMMER SWITCH - A switching device includes a paddle actuator biased to a rest position and configured to pivot relative to a housing to a depressed position to engage an air-gap switch disposed within the housing. The air-gap switch is configured to change a first state of a load connected to the switching device upon engagement by the paddle actuator. The paddle actuator is defined by a pair of opposing long sides and a pair of opposing short sides and has at least one slot defined therein parallel to the pair of opposing short sides thereof and centrally disposed between the pair of opposing long sides thereof. A rocker actuator is disposed in the at least one slot defined in the paddle actuator and is configured to pivot relative thereto to engage at least one switch. The at least one switch is configured to change a second state of the load connected to the switching device upon engagement by the rocker actuator. | 07-30-2009 |
20100101924 | SWITCHING DEVICE - A switching device includes a housing and a paddle actuator operably coupled to a front face of the housing and adapted to control a state of a load. The paddle actuator has a pair of opposing long sides and short sides and is configured to pivot about a hinge disposed proximate to one of the short sides of the paddle actuator. At least one component is disposed adjacent to the short side of the paddle actuator that is disposed proximate to the hinge and is configured to sense at least one condition. A control element is configured to control at least one of a sensing range and a sensitivity of the at least one component. The paddle actuator occupies at least 50% of the front face of the housing and the at least one component substantially occupies the remainder of the front face. | 04-29-2010 |
20110062896 | DIGITAL WIRING DEVICE - A digital wiring device including a user interface panel, a digital display, and a paddle including a transparent portion to reveal the digital display and an opaque portion to cover the user interface panel. The paddle rotates from a first closed position to a second open position. A digital “schedule-at-a-glance” may be provided so that a user can quickly assess a schedule of events. The digital wiring device may include a back light to illuminate the digital display. The paddle may be operatively associated with the back light. A battery may provide an electrical current to power the digital wiring device in a battery backup mode, and the back light may be disabled based on the mode. The user interface panel may be used to schedule events or otherwise configure the digital wiring device. | 03-17-2011 |
Chun-Ting Chou, Elmsford, NY US
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20080259847 | Coordinated Beacon Period (Bp) Mergins for Distributed Wireless Networks - The application describes a method to merge two wireless networks in which each terminal gets a beacon slot within the beacon period. In order to merge two networks, the beacon slots have to be time-coordinated such that the beacon slots of the first network are completed before the beacon slots of the second network begin. The method includes transmitting a beacon frame having a beacon period switch information element which instructs the neighboring terminals in the first network of the need to merge, provides clock synchronization information; provides the time of the merge; and informs the neighboring terminals which beacon slot to occupy in the beacon period of the merged network. In order to deal with hidden terminals, the information needs to be forwarded terminal-to-terminal within each network. | 10-23-2008 |
Chun-Ting Chou, Briarcliff Manor, NY US
Patent application number | Description | Published |
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20080310348 | Wireless Systems and Methods Including Cooperative Communication Medium Access Control - A complementary medium access control (CMAC) method and apparatus are described. | 12-18-2008 |
20090073924 | METHOD OF DISCOVERING AN AD-HOC ON-DEMAND DISTANCE VECTOR ROUTE HAVING AT LEAST A MINIMUM SET OF AVAILABLE RESOURCES IN A DISTRIBUTED WIRELESS COMMUNICATIONS NETWORK - In a wireless communication network ( | 03-19-2009 |
20090092105 | METHOD OF RESERVING RESOURCES WITH A MAXIMUM DELAY GUARANTEE FOR MULTI-HOP TRANSMISSION IN A DISTRIBUTED ACCESS WIRELESS COMMUNICATIONS NETWORK - In a communication network ( | 04-09-2009 |
20100020739 | AUTOMATIC PARTNER SELECTION IN THE COOOPERATIVE MAC PROTOCOL - The present invention provides a system ( | 01-28-2010 |
20100290387 | AUTOMATIC CANCELLATION OF BP MERGER IN MULTI-BAND OFDM ALLIANCE (MBOA) ULTRA WIDE BAND (UWB) SYSTEMS - The current MBOA UWB MAC protocol requires a device that detects alien devices to include a BP Switch IE in its beacon so that its neighbors may learn the presence of the alien devices and follow that device to relocate their beacons in a coordinated fashion. However, during the transition period of beacon relocation, that device may decide to halt the relocation process as required by the standard and such decisions also have to be received by its neighbors. In such a case, a BP switch IE will be generated by that device which includes a BPST offset equal to a length of a superframe. | 11-18-2010 |
Chun-Ting Chou, Croton-On-Hudson, NY US
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20100135224 | DEVICE DISCOVERY FOR MIXED TYPES OF DIRECTIONAL TERMINALS - An antenna ( | 06-03-2010 |
Eunice Chou, New York, NY US
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20090222511 | DELIVERING COMPOSITE MEDIA TO A CLIENT APPLICATION - An approach is provided for generating composite media and delivering the composite media to a client application. Data is received from one or more external sources, and a portion of the data is selected to be used in the composite media according to the time period of delivery of the client application, user information, or the type of client application requesting the media, if a request has been made. The selected data is integrated into a pre-created template to generate the composite media, such as an advertisement, special offers, or weather and stock information. The composite media may be modified prior to being delivered to the client application. The selection of the pre-created template and the modification of the composite media are made according to requirements of the client application, user information, or the type of client application (e.g., gaming application) requesting the media. | 09-03-2009 |
Hung-Kuo Chou, New York, NY US
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20090022811 | Mineralized guided bone regeneration membranes and methods of making the same - The present invention provides a method for mineralizing commercially available guided bone regeneration membranes. The method comprises the steps of (a) providing a commercially available guided bone regeneration membrane, (b) applying a mineralizing solution, and (c) microwaving the membrane. The method may further comprise (d) rinsing the membrane in a solution such as distilled water and (e) drying the membrane. The mineralizing solution may be a solution capable of supplying or delivering a mineral such as calcium or zinc. The invention further provides guided bone regeneration membranes made by the methods described. The guided bone regeneration membrane comprises a mineral, such as, for instance calcium or zinc at a weight percent of at least 5%, at least 10%, at least 12%, at least 15%, at least 18%, at least 20% or at least 25% (weight percent) of the membrane. Further, the invention provides methods for enhancing bone regeneration and methods for inhibiting bacterial infection and inflammation. | 01-22-2009 |
Kevin Ying Chou, Painted Post, NY US
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20090143219 | Stabilizers for ceramic body extrusion - A mixture for making a ceramic article includes a ceramic forming component, a liquid vehicle, a cellulosic binder, and a stabilizer comprising an acetate salt. The disclosure also provides a method of making the ceramic article including extruding the mixture to form a ceramic green body, drying the ceramic green body to remove at least a portion of the liquid vehicle, and optionally firing to form the ceramic article. The ceramic green body possesses excellent strength and excellent skin properties without increasing the organic load or the addition of hydrated clays. | 06-04-2009 |
20100113249 | ALKYLCELLULOSE SALT BINDER FOR GREEN BODY MANUFACTURE - A batch mixture including ceramic-forming ingredients, a pore former, a binder comprising an ammonium salt of an alkylated cellulose binder, and a liquid vehicle, as defined herein. Also disclosed is a method for producing a ceramic precursor article as defined herein having excellent extrusion properties. | 05-06-2010 |
20120135854 | Method of Forming Porous Ceramic Articles Using Inert Gas - A method of manufacturing a porous ceramic article is provided that includes injecting a gas into a precursor batch material. The gas is pressurized to a positive gauge pressure. Exemplary gasses that can be injected into the precursor batch material include at least one of nitrogen, helium, neon, argon, krypton, and xenon. Air can also be injected into the precursor batch material, including air in which at least a portion of CO | 05-31-2012 |
20120299227 | Compositions and Methods for Making Low Thermal Expansion Ceramic Bodies - Comminuted pre-mixtures for technical ceramics production, and ceramic bodies made therefrom, the comminuted pre-mixtures being comprised of cellulosic components and alumina source components and the bodies being produced by compounding the comminuted pre-mixtures with powdered inorganic components into batch mixtures, adding liquids to the batch mixtures to form plastic batches, forming the plastic batches into shaped bodies, and heating the shaped bodies to form the ceramic bodies. | 11-29-2012 |
20130072370 | Methods for Reducing Defects in Ceramic Articles and Precursors - A method of reducing the defects in ceramic articles and precursors, particularly ceramic articles and precursors made using a batch composition containing an oil phase material. The method includes increasing the concentration of a water insoluble soap in the batch composition, which can increase the cohesive strength of the oil phase, leading to a reduction in the incidence of defects in the ceramic articles and precursors. | 03-21-2013 |
Sharon Hsiao-Wei Chou, Great Neck, NY US
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20100287517 | Statistical Static Timing Analysis in Non-Linear Regions - A method is described for simulating the f-sigma timing path delay of an integrated circuit design when local transistor variations determine the stochastic delay. This is achieved by determining an estimated delay time for a first timing path using non-linear operating point analysis of local variations (NLOPALV). An operating point is calculated for each cell that is included in a timing path in the integrated circuit design. The f-sigma operating point of a cell-arc is a point on the cell-arc delay function (CADF). An f-sigma delay value is determined for each cell using the selected operating point on the CADF of the cell. The determined delay values of the plurality of cells in the timing path may then be combined to predict the estimated delay for the entire timing path. The method may be extended to deal with slew rate, predict hold time statistics, prune paths, and deal with convergent paths. | 11-11-2010 |
Tim Chou, Syosset, NY US
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20090037561 | Automatically Adjusting Command Parameters To Support Devices Of A Computer Network - Adjusting one or more command parameters for a device of a computer network includes accessing command sets. A command set comprises one or more commands supported by a known device, and a command has one or more command parameters. One or more command sets associated with an unknown device are identified. The following are repeated for each command set of the one or more command sets until a termination event occurs: applying the command set to the unknown device to perform an operation; determining whether the command set has failed to perform the operation; and automatically adjusting the command parameters of the command set if the command set has failed to perform the operation. | 02-05-2009 |