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| 20100109717 | Pixel Circuit - A pixel circuit includes an LED having an anode that receives a driving current and a cathode that receives a scan signal, and a driving circuit including: a switch unit operable according to a voltage signal, and adapted for permitting transfer of a data signal when operating in an on state; a capacitor having a first end coupled to the switch unit, and a second end; a first transistor having a first terminal that is coupled to the second end of the capacitor, a second terminal that is coupled to the anode of the LED, and a control terminal that is coupled to the first end of the capacitor; and a second transistor having a first terminal that is adapted for coupling to the voltage source, a second terminal that is coupled to the first terminal of the first transistor, and a control terminal that is adapted for receiving a reference voltage. | 05-06-2010 |
| 20110205221 | DISPLAY AND COMPENSATION CIRCUIT THEREFOR - A display includes a scan line, a data line, a pixel circuit, a compensation circuit, a voltage controller, and a data line driver. The data line forms a junction with the scan line. The pixel circuit is disposed at the junction of the scan line and the data line. When the scan line and the data line are driven, the pixel circuit generates a driving current. The compensation circuit generates a comparing signal and a positioning signal based on the driving current. The voltage controller generates a reference voltage that corresponds to the positioning signal with reference to the comparing signal. The data line driver corrects an image signal based on the reference voltage, and drives the data line with the corrected image signal. A compensation circuit for the display is also disclosed. | 08-25-2011 |
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| 20090039925 | SAMPLE-AND-HOLD AMPLIFICATION CIRCUITS - A sample-and-hold amplification circuit comprises an amplifier, a first sample-and-hold unit, and a second sample-and-hold unit. The amplifier has an input terminal and an output terminal. The first sample-and-hold unit is coupled to the input terminal and the output terminal. The second sample-and-hold unit is coupled to the input terminal and the output terminal. When the first sample-and-hold unit is arranged to perform a sampling operation, the second sample-and-hold unit performs a holding operation, and when the first sample-and-hold unit is arranged to perform the holding operation, the second sample-and-hold unit performs the sampling operation. | 02-12-2009 |
| 20090195315 | SAMPLE-AND-HOLD AMPLIFIERS - A sample-and-hold amplifier is provided. The sample-and-hold amplifier comprises a sample-and-hold circuit and a buffer circuit. The sample-and-hold circuit receives an input signal and transmits the input signal to a first node according to a control signal. The buffer circuit is coupled between a supply voltage source and a ground and controlled by the first node to provide an output signal at an output node. The buffer circuit comprises a native MOS transistor coupled to the output node. | 08-06-2009 |
| 20100127910 | COMPARATOR AND PIPELINED ADC UTLIZING THE SAME - A comparator includes a plurality of switches, a capacitor, an amplifier, and a latch. The switches provide an input signal during a first period and provide a reference signal during a second period. A first switch among the switches is composed of a first transistor. The capacitor receives the input signal during the first period and receives the reference signal during the second period. The amplifier is coupled to the capacitor for receiving a difference voltage between the input signal and the reference signal and amplifies the difference voltage during the second period to generate an amplified result. The determining circuit provides a digital signal according to the amplified result. | 05-27-2010 |
| 20100182173 | FLIP-FLOP AND PIPELINED ANALOG-TO-DIGITAL CONVERTER UTILIZING THE SAME - A flip-flop includes a sense amplifier stage and a latch stage. The sense amplifier includes a first P type transistor and generates a first sensed signal and a second sensed signal in a first node and a second node, respectively. When the first P type transistor is turned on, the first node is connected to the second node. The latch stage generates a first output signal and a second output signal according to the first and the second sensed signals. | 07-22-2010 |
| 20100182179 | PIPELINED ANALOG-TO-DIGITAL CONVERTER - A pipelined analog-to-digital converter includes at least one multiplying digital-to-analog converter and at least one sub-ADC. The multiplying digital-to-analog converter includes at least one first capacitor, at least one second capacitor, an amplifier, and a plurality of switches. The amplifier is coupled to the first and the second capacitors. The switches control a connection between the first and the second capacitors according to a first control signal, a second control signal and a digital signal. In a first period, the first capacitor is connected to the second capacitor in parallel. In a second period, the first capacitor is connected to the second capacitor in series. At least one switch among the switches is composed of a transistor. The sub-ADC provides a digital signal according to the first and second control signals. | 07-22-2010 |
| 20100328129 | PIPELINE ANALOG-TO-DIGITAL CONVERTER WITH PROGRAMMABLE GAIN FUNCTION - A pipeline analog-to-digital converter (ADC) comprises a plurality of pipeline stages is disclosed. The first pipeline stage has programmable gain function. The first pipeline stage includes a sub-analog-to-digital converter (sub-ADC) and a multiplying digital-to-analog converter (MDAC) implemented by switched capacitor (SC) circuits. Different capacitances in the sub-ADC and MDAC are provided so as to provide different gains by controlling switches in the SC circuits. | 12-30-2010 |
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| 20100244220 | LAYOUT STRUCTURE AND METHOD OF DIE - A layout structure and layout method are provided. The layout structure includes a first conductive via, a second conductive via, a die and eight pads. The first conductive via and the second conductive via pass through the die. The first conductive via has a first pad and a second pad, and the second conductive via has a third pad and a fourth pad. A fifth pad is conducted to the third pad. A sixth pad is conducted to the second pad. A seventh pad is conducted to the first pad. An eighth pad is conducted to the fourth pad. In a vertical direction of the die, the first pad and the second pad are overlapped, the third pad and the fourth pad are overlapped, the fifth pad and the sixth pad are overlapped, and the eighth pad and the seventh pad are overlapped, partially or totally. | 09-30-2010 |
| 20100289139 | HARDWIRED SWITCH OF DIE STACK AND OPERATING METHOD OF HARDWIRED SWITCH - A hardwired switch of a die stack including eight landing pads is provided. A first, a second, a third, and a fourth landing pads are disposed on a first surface of a die. The second and the fourth landing pads are electrically connected to the first and the third landing pads respectively. A fifth, a sixth, a seventh, and an eighth landing pads are disposed on a second surface of the die. The seventh and the eighth landing pads are electrically connected to the sixth and the fifth landing pads respectively. In a vertical direction of the die, the first, the second, the third, and the fourth landing pads overlap partially or fully with the fifth, the sixth, the seventh, and the eighth landing pads respectively. In addition, an operating method of a hardwired switch is also provided. | 11-18-2010 |
| 20100295189 | METHOD FOR REPAIRING CHIP AND STACKED STRUCTURE OF CHIPS - A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block with a second function, and a signal path electrically connected to the first and the second circuit blocks. A second chip is provided, which includes a third circuit block with the first function. The functions of the first and the second chips are verified. The first circuit block is disabled if the first circuit block is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the second circuit block is functional and the third circuit block is functional. | 11-25-2010 |
| 20100320565 | WAFER AND METHOD FOR IMPROVING YIELD RATE OF WAFER - A wafer and a method for improving the yield rate of the wafer are provided. The wafer includes a first and a second circuit units, a first and a second through silicon vias (TSVs), and a first spare TSV. The first and the second circuit units are disposed inside the wafer. The first TSV vertically runs through the wafer and is coupled to the first circuit unit through the front metal of the wafer. The second TSV vertically passes through the wafer and is coupled to the second circuit unit through the front metal of the wafer. When the first or the second TSV has failed, the first spare TSV vertically passes through the wafer to replace the failed first or second TSV. | 12-23-2010 |
| 20110006829 | ISOLATION CIRCUIT - An isolation circuit is provided. The isolation circuit is coupled to an output and an input node and includes a first set, a second switch set, and a body bias voltage generator. The first switch set couples a switch control node to a second voltage when a first voltage is at a first voltage level, and couples the switch control node to the input node when the first voltage is at a second voltage level. The second switch set couples the output node to the input node when the first voltage is at the first voltage level, and isolates the output node from the input node when the first voltage is at the second voltage level. The body bias voltage generator selectively provides a higher one of the first voltage and a voltage on the input node to a body of the second switch set. | 01-13-2011 |
| 20110080184 | METHOD FOR TESTING THROUGH-SILICON-VIA AND THE CIRCUIT THEREOF - The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty. | 04-07-2011 |
| 20110080185 | METHOD FOR TESTING THROUGH-SILICON-VIA AND THE CIRCUIT THEREOF - The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty. | 04-07-2011 |
