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| 20090057894 | Structure of Gold Bumps and Gold Conductors on one IC Die and Methods of Manufacturing the Structures - A method for fabricating multiple metal layers includes the following steps. An electronic component is provided with multiple contact points. A first metal layer is deposited over said electronic component. A first mask layer is deposited over said first metal layer. A second metal layer is deposited over said first metal layer exposed by an opening in said first mask layer. Said first mask layer is removed. A second mask layer is deposited over said second metal layer. A third metal layer is deposited over said second metal layer exposed by an opening in said second mask layer. Said second mask layer is removed. Said first metal layer not covered by said second metal layer is removed. | 03-05-2009 |
| 20090057900 | Stacked Chip Package With Redistribution Lines - A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate. | 03-05-2009 |
| 20090104769 | Semiconductor chip with coil element over passivation layer - A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer. | 04-23-2009 |
| 20090108453 | CHIP STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer. | 04-30-2009 |
| 20090111261 | Over-passivation process of forming polymer layer over IC chip - A method for forming a semiconductor chip or wafer includes following steps. A semiconductor substrate is provided, and then a polymer layer is deposited over the semiconductor substrate, wherein the polymer layer comprises polyimide. The polymer layer with a temperature profile having a peak temperature between 200 and 320 degrees Celsius. Alternatively, the temperature profile may comprises a period of time with a temperature higher than 320 degree Celsius, wherein the period of time is shorter than 45 minutes. | 04-30-2009 |
| 20110233776 | SEMICONDUCTOR CHIP WITH COIL ELEMENT OVER PASSIVATION LAYER - A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer. | 09-29-2011 |
| 20110241183 | STACKED CHIP PACKAGE WITH REDISTRIBUTION LINES - A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate. | 10-06-2011 |
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| 20080219035 | Active Power Filter - An active power filter comprises an energy storage capacitor, an inverter, a filtering circuit and a controller. The inverter is controlled to act as a virtual resister at a fundamental frequency for compensating for the power loss of the active power filter, act as a virtual capacitor at a fundamental frequency for compensating for a fundamental reactive power of the load, and/or generate a harmonic current for suppressing the harmonic currents of specific orders of the load. | 09-11-2008 |
| 20080253153 | Active Power Conditioner - An active power conditioner includes a first power electronic switch set, a second power electronic switch set, a third power electronic switch set, an input filter and an output filter. The active power conditioner can supply a stable AC voltage to a load when a voltage variation is occurred at an AC power source by controlling either the second power electronic switch set or the third power electronic switch set via high-frequency switching, and the other power electronic switch sets that are not switched in high frequency are controlled to switch in low-frequency switching. | 10-16-2008 |
| 20090174260 | UPS System having a Function of Parallel Operation - A UPS system includes one or more UPS units with identical or different capacities. A control circuit, used to control a DC/AC inverter of the UPS unit, includes a voltage feedback control circuit and a current feedforward control circuit. The voltage feedback control circuit is used to control the amplitude and the waveform of load voltage. The current feedforward control circuit is used to operate the DC/AC inverter of the UPS unit as a virtual fundamental resistor and a virtual harmonic resistor which are serially connected to an output terminal of the DC/AC inverter such that each UPS unit can be distributed to provide an output current according to the capacity ratio of the UPS system. | 07-09-2009 |
| 20100072819 | Bi-directional DC to DC power converter having a neutral terminal - A bidirectional DC to DC power converter includes two DC sources, two inductors respectively connected to the two DC sources, a first switch and a second switch respectively connected to the two inductors, two capacitors respectively connected to the two switches, and a third switch connected between the two inductors. The first, second and third switches are respectively connected reversely with a diode in parallel. When the third switch is alternately turned on and off and the first and second switches are always turned off, the power converter operates as a boost power converter and electric energy flows from the two DC sources to the two capacitors. When the third switch is always turned off and the first and second switches are synchronously turned on or off, the power converter operates as a buck power converter and electric energy flows from the two capacitors to the two DC sources. | 03-25-2010 |
| 20100085784 | Ripple Voltage Suppression Method for DC/DC Converter and Apparatus Thereof - A ripple voltage suppression apparatus includes a DC/DC converter and a control circuit. The DC/DC converter has a power electronic switch. The control circuit has a voltage detector detecting a DC output voltage of the DC/DC converter, a ripple voltage suppression circuit receiving the detected DC output voltage to generate an AC control signal for controlling an AC component of a duty ratio of the power electronic switch, an output voltage regulation circuit receiving the detected DC output voltage to generate a DC control signal for controlling an DC component of a duty ratio, an adder adding the AC and DC control signals to form a combined control signal, and a PWM circuit converting the combined control signal into a PWM signal to control the power electronic switch. Only the DC output voltage of the DC/DC converter has to be detected for the control circuit. | 04-08-2010 |
| 20100201341 | Three-Leg Power Converter Apparatus - A three-leg power converter apparatus including first, second and third input/output ports, a three-leg bridge converter, a filter circuit, a decoupling circuit and a controller is presented. The three-leg bridge converter has three single-leg circuits, two DC terminals connecting to two terminals of the first input/output port, and three mid-terminals with each of them being formed by a middle point of one of the three single-leg circuits. The controller connects to the three-leg bridge converter for controlling an input or output current passing through each DC terminal and mid-terminal. The filter circuit connects between two of the mid-terminals and the second input/output port. The decoupling circuit has two terminals connecting to the second input/output port and another terminal connecting to a terminal of the third input/output port, with the third input/output port having another terminal connecting to the other mid-terminal that dose not connect with the filter circuit. | 08-12-2010 |
| 20110260692 | Estimation Method for Residual Discharging Time of Batteries - An estimation method for residual discharging time of batteries includes the steps of: providing a set of battery-discharge-current intervals and a set of battery-discharge equations, setting discharge time of each battery-discharge-current intervals zero; detecting a discharge current, voltage and time of batteries; judging whether the discharge current exceeding all of the battery-discharge-current intervals; selecting one of the battery-discharge-current intervals and the associated battery-discharge equation according to the detected discharge current; calculating an estimation of residual discharging time; accumulating and recording the discharge time; judging whether the discharge voltage being lower than a predetermined value and calculating an estimation error of the residual discharging time; adjusting parameters of the battery-discharge equation for reducing the estimation error of the residual discharging time if the estimation error is greater than a predetermined error value. | 10-27-2011 |
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| 20100086871 | PHOTOSENSITIVE POLYIMIDES - The invention pertains to an epoxy-modified photosensitive polyimide, which possesses excellent heat resistance, chemistry resistance, and flexibility, and can be used in a liquid photo resist or dry film resist, or used in a solder resist, coverlay film, or printed circuit board. | 04-08-2010 |
| 20100086874 | Photosensitive polymides - The invention pertains to an isocyanate-modified photosensitive polyimide. The photosensitive polyimide of the invention possesses excellent heat resistance, chemical resistance and flexibility, and can be used in a liquid photo resist composition or dry film photo resist composition, or used in a solder resist, coverlay film, or printed wiring board. | 04-08-2010 |
| 20100297455 | PRECURSOR SOLUTION FOR POLYIMIDE/SILICA COMPOSITE MATERIAL, ITS MANUFACTURE METHOD, AND POLYIMIDE/SILICA COMPOSITE MATERIAL HAVING LOW VOLUME SHRINKAGE - The present invention relates to a process for preparing a precursor solution for polyimide/silica composite material and a process for forming a polyimide/silica composite material film on a substrate, comprising adding a monomer of a silane compound to allow a poly(amic acid) to carry a silica moiety; adding a monomer of formula (R | 11-25-2010 |
| 20110212402 | PHOTOSENSITIVE RESIN COMPOSITION AND ITS APPLICATION - A photosensitive resin composition comprising:
| 09-01-2011 |
