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Chou, Hsinchu City
Charlie Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100067694 | FILE-TRANSMITTING METHOD AND SCANNING DEVICE USING THE SAME - A file-transmitting method and a scanning device are provided. A document is scanned and an image file of the document is generated. The image file is stored to a remote storage device. File-access data for accessing the image file is generated. The file-access data is transmitted to a receiving destination. The scanning device includes a scanning head assembly, a processing unit and a transmitting unit. The scanning head assembly scans a document and generates an image file of the document. The processing unit, electrically coupled to the scanning head assembly, processes the image file and generates file-access data for accessing the image file. The transmitting unit, electrically coupled to the processing unit, transmits and stores the image file to a remote storage device, and transmits the file-access data to a receiving destination. | 03-18-2010 |
Cheng-Wei Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120018718 | Self-aligned top-gate thin film transistors and method for fabricating same - A self-aligned top-gate thin film transistor and a fabrication method thereof. The method includes preparing a substrate having sequentially formed thereon an oxide semiconductor layer, a dielectric layer, and a metallic layer, wherein the oxide semiconductor layer includes first and second connecting regions that are not covered by the dielectric layer and the metallic layer thereon respectively, the first and second connecting regions having a property of a conductor after undergone a heating process or an ultraviolet irradiation; and a source electrode and a drain electrode formed on the substrate and connected to the first and second connecting regions, respectively. Therefore, the contact resistance of the first and second connecting regions can be reduced without the process of ion dopants as required by prior art techniques, thereby simplifying the manufacturing process. Also, the source electrode and the drain electrode can be exactly relocated and further increase performance of the device. | 01-26-2012 |
Chih-Rong Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090195519 | Image processing apparatus - An image processing apparatus comprises a display module, a control module and a scroll wheel module. The display module is used to display a digital image. The control module is connected to the display module for controlling the display module and conducting image processing. The scroll wheel module is connected to the control module for providing at least five operation modes, each in a different direction, and generating at least five control signals for controlling the control module to conduct image processing. | 08-06-2009 |
Chuen Shyong Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110291032 | ELECTROMAGNETIC SHIELDING COMPOSITION, ELECTROMAGNETIC SHIELDING DEVICE, ANTI-ELECTROSTATIC DEVICE AND METHOD OF MANUFACTURING ELECTROMAGNETIC SHIELDING STRUCTURE - An electromagnetic shielding composition includes a carrier, a plurality of metal nanowires, and a plurality of nanoparticles. The plurality of metal nanowires are dispersed within the carrier and are in an amount of from 1 to 95 percent by weight of the electromagnetic shielding composition. The plurality of nanoparticles are dispersed within the carrier and are in an amount of from 0.5 to 60 percent by weight of the electromagnetic shielding composition. | 12-01-2011 |
Chun-Yi Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110292022 | POWER CONVERTING APPARATUS AND POWER CONVERTING METHOD - A power converting apparatus including a power converting unit and a control unit is provided. The power converting unit receives an input voltage and generates an output voltage for a display driving unit according to a control signal. The control unit provides the control signal to the power converting unit, wherein the control unit adjusts the duty cycle or the frequency of the control signal according to an image signal. In addition, a power converting method is also provided. | 12-01-2011 |
| 20120293473 | DISPLAY APPARATUS AND IMAGE COMPENSATING METHOD THEREOF - A display apparatus is disclosed. The display apparatus includes an environment luminance detector, a display image data analyser, and an image compensation processor. The environment luminance detector detects an environment luminance and generates an environment luminance grade according to the environment luminance. The display image data analyser receives display image data and analyses a luminance of the display image data to generate a display image data luminance grade. The image compensation processor generates an image luminance enhancement value, an image color compensating value and an image edge enhancement value. The image compensation processor compensates the display image data to generate compensated image data according to the image luminance enhancement value, the image color compensating value and the image edge enhancement value. | 11-22-2012 |
| 20130044088 | DATA TRANSMISSION METHOD AND DISPLAY DRIVING SYSTEM - A data transmission method applied in a display, which includes a display panel, is provided. The data transmission method includes the following steps of: providing a host controller and n display drivers, n is a natural number greater than 1; providing a communication link under mobile industry processor interface (MIPI), connecting the host controller to the n display drivers; determining n virtual channel values Vc1-Vcn corresponding to the respective n display drivers; employing the host controller for providing a command with a virtual channel parameter through the communication link under MIPI; when the virtual channel parameter corresponds to an i | 02-21-2013 |
| 20130044089 | DATA TRANSMISSION METHOD AND DISPLAY DRIVING SYSTEM - A data transmission method applied in a display, which includes a display panel, is provided. The data transmission method includes the following steps of: providing a host controller and n display drivers, n is a natural number greater than 1; providing a communication link under mobile industry processor interface (MIPI), connecting the host controller to the n display drivers; determining n virtual channel values Vc | 02-21-2013 |
Fong-In Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100150828 | RADIOACTIVE GOLD NANOPARTICLES AND METHODS OF MAKING AND USING THEM - Methods of preparing a composition comprising non-ionic, radioactive gold nanoparticles (R-GNPs) are disclosed. The method comprises: a) providing a solution comprising gold (Au-197) ions; and b) exposing the solution to neutron irradiation to generate a composition comprising non-ionic R-GNPs. Alternatively, the method comprises: a) providing a solution that comprises a composition comprising gold (Au-197) nanoparticles (GNPs); and b) exposing the GNP solution to neutron irradiation to generate a composition comprising non-ionic R-GNPs. Compositions that comprises non-ionic R-GNPs encapsulated within and/or anchored to MSNs, and methods of making the same are also disclosed. | 06-17-2010 |
Han-Hwa Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100163105 | SOLAR CELL PACKAGE TYPE WITH SURFACE MOUNT TECHNOLOGY STRUCTURE - A solar cell package type with surface mount technology structure, comprising: a solar cell having a first electric terminal at the bottom thereof and a second electric terminal at the top thereof; at least a connection electric terminal capped at both sides of the solar cell in such a way that the top of the connection electric terminal is connected to the second electric terminal; and at least an insulation layer capped at both sides and partially placed at the bottom of the solar cell in such a way that it is interposed between the electric terminal and the solar cell for avoiding the short current and the water penetration. In this way, this package in accordance with the invention tends to increase the array density of the solar cells on the substrate and to minimize the manufacturing cost. | 07-01-2010 |
Huitsuo Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090040304 | OPTICAL FIBER SECURITY SYSTEM - An optical fiber security system is described. The optical fiber security system includes an optical fiber, an optoelectronic modulator and an optoelectronic demodulator. The optoelectronic modulator and the optoelectronic demodulator are both directly connected to the optical fiber. The optoelectronic modulator converts video signals to cable television video signals and subsequently converts to optical signals. The optical signals are transmitted to the optoelectronic demodulator through the optical fiber. The optoelectronic demodulator further reverses the optical signals back to the video signals to remotely monitor the environment. | 02-12-2009 |
I-Fang Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100185305 | MONITORING CIRCUIT, MONITORING DEVICE AND MONITORING METHOD THEREOF - A monitoring device for monitoring an abnormal load or unload operation of a wafer. The monitoring device includes a sensing unit and a detective unit. The sensing unit is for providing a sensing information, which indicates whether the wafer protrudes from a side of a carrier. The detective unit is for determining whether a duration, for which the wafer protrudes from the side of the carrier exceeds a predetermined time, for which the wafer is loaded or unloaded, according to the sensing information. If the duration exceeds the predetermined time, the detective unit further triggers an abnormal event. | 07-22-2010 |
Jih-Wen Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080233706 | MANUFACTURING METHOD OF DYNAMIC RANDOM ACCESS MEMORY - A dynamic random access memory (DRAM) is provided. The dynamic random access memory includes a deep trench capacitor disposed in a first trench of a substrate, a conductive layer disposed in a second trench of the substrate, a gate structure, and a conductive layer disposed on the surface of the substrate at two sides of the gate structure. The depth of the second trench is smaller than the depth of the first trench, and the second trench partially overlaps with the first trench. The conductive layer disposed in the second trench is electrically connected with the conductive layer of the deep trench capacitor. The gate structure is disposed on the substrate. The conductive layer at one side of the gate structure is electrically connected with the conductive layer disposed in the second trench. | 09-25-2008 |
Kai-Hsiang Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090103752 | DEVICE AND METHOD FOR AUTOMATICALLY ADJUSTING GAIN - A device and method are provided for automatically adjusting gain, including a conversion module for converting an audio time-domain signal to an audio frequency-domain signal, an analysis module for analyzing the audio frequency-domain signal in accordance with an equal-loudness level contour of human hearing so as to generate strength weightings and generating a signal strength in accordance with the weightings, a calculation module for calculating a gain by analysis of the audio frequency-domain signal when the signal strength falls outside a default range, and a control module for generating an audio output signal in accordance with the gain and the audio time-domain signal. | 04-23-2009 |
| 20090257335 | AUDIO SIGNAL PROCESSING METHOD - An audio signal processing method includes the steps of: dividing an audio signal data stream into a plurality of selection segments; determining a target segment in the audio signal data stream, the target segment including a splice point for splicing a splice segment thereto; selecting one of the selection segments as the splice segment according to at least one parameter of the target segment; and processing the target segment and the splice segment to splice the splice segment to the target segment, and outputting a processed segment. | 10-15-2009 |
Kan-San Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110097842 | Method for preparing IGZO particles and method for preparing IGZO film by using the IGZO particles - A method for preparing IGZO particles and a method for preparing an IGZO thin film by using the IGZO particles are disclosed. The method for preparing the IGZO particles comprises the following steps: (A) providing a solution of metal acid salts, which contains a zinc salt, an indium salt, and a gallium salt; (B) mixing the solution of the metal acid salts with a basic solution to obtain an oxide precursor; and (C) heating the oxide precursor to obtain IGZO particles. | 04-28-2011 |
Kan-Sen Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100166633 | CATALYST AND METHOD FOR DECOMPOSING VOLATILE ORGANIC COMPOUNDS - A catalyst for decomposing volatile organic compounds is provided. The catalyst includes a mesoporous material and silver carried by the mesoporous material. The invention also provides a method for decomposing volatile organic compounds. The method includes providing a gas containing volatile organic compounds and contacting the gas containing volatile organic compounds and the disclosed catalyst to decompose and oxidize the gas containing volatile organic compounds into carbon dioxide and water. | 07-01-2010 |
| 20110020534 | BATTERY ELECTRODE MAKING METHOD - A manufacturing method of a battery electrode includes the following steps: providing a reducing reagent, a conductive adjuvant, and a solution comprising ferric ion, wherein the conductive adjuvant is selected from the group consisting of a metallic salt, a metal particle, a metal compound and a carbon conductive substance; applying the conductive adjuvant into the solution comprising ferric ion to form a first mixture solution, followed by mixing the first mixture solution with the reducing reagent to form a second mixture solution, wherein the conductive adjuvant and the ferric ion are reduced by the reducing reagent to form a composite micro-particle comprising iron micro-particle; isolating the composite micro-particle from the second mixture solution; providing an adhesive reagent and mixing with the composite micro-particle to form a coating reagent; and applying the coating reagent onto a metal mesh to produce the battery electrode. | 01-27-2011 |
Kuan-Hung Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080201451 | SYSTEMS AND METHODS FOR REAL-TIME MEDIA COMMUNICATIONS - A system for real-time media communication comprises a first server unit configured to interface between at least one user and a blog and a second server unit configured to process the real-time media content in a streaming mode. The first server unit comprises a publishing control module configured to identify an identity of a publisher of the at least one user, allow the publisher to transmit real-time media content if the identity of the publisher is authentic and receive a description of the real-time media content from the publisher, and a link module configured to obtain a location of the real-time media content so that the location of the real-time media content is accessible to the at least one user. The second server unit comprises a receiving module configured to receive the real-time media content, a recording module configured to record the real-time media content, and a dispatching module configured to provide the location of the real-time media content to the publishing module. | 08-21-2008 |
Kuo-Yu Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120044398 | CMOS SENSOR WITH LOW PARTITION NOISE AND LOW DISTURBANCE BETWEEN ADJACENT ROW CONTROL SIGNALS IN A PIXEL ARRAY - A CMOS image sensor includes a pixel array including a plurality of unit pixels with individual rows of unit pixels being coupled to respective row control signal lines, and a buffer including plural row control signal drivers. Each driver is coupled to a respective one of the row control signal lines and is configured to provide a row control signal pulse to a respective row control signal line in response to an input pulse when the row control signal line is in an active state and to bias the row control signal line at a ground voltage when the respective row control signal line is in an inactive state. Each driver has a first drive capability when the row control signal line is in the active state and a second drive capability greater than the first drive capability when the row control signal line is in an inactive state. | 02-23-2012 |
| 20120098975 | COLOR IMAGE SENSOR ARRAY WITH COLOR CROSSTALK TEST PATTERNS - An integrated circuit comprises a semiconductor substrate and a color image sensor array on the substrate. The color image sensor array has a first configuration of color pixels for collecting color image data, and at least one crosstalk test pattern on the substrate proximate the color image sensor array. The crosstalk test pattern includes a plurality of color sensing pixels arranged for making color crosstalk measurements. The test pattern configuration is different from the first configuration. | 04-26-2012 |
Mei-Ling Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120043555 | LIQUID FLUORESCENT COMPOSITION AND LIGHT EMITTING DEVICE - The invention provides a liquid fluorescent composition. The liquid fluorescent composition includes at least (a) 0.001-2 parts by weight of a fluorescent material; and (b) 100 parts by weight of a cyclic solvent having a boiling point above 100° C. The invention also provides a light emitting device containing the above liquid fluorescent composition. | 02-23-2012 |
Min-Chung Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090146726 | DELAY CIRCUIT WITH CONSTANT TIME DELAY INDEPENDENT OF TEMPERATURE VARIATIONS - A delay circuit has: an inverting receiver with a resistive element, the inverting receiver having an input node for receiving an input signal and an output node coupled to the resistive element; a capacitive element, coupled to the output node of the inverting receiver and the resistive element; a first transistor, having lower turned ON voltage at higher temperature; a second transistor, used for generating a rail to rail signals on a terminal of the first transistor; and an output inverter, having an input node coupled to the first transistor and an output node for outputting an output signal of the delay circuit. Further, a third transistor is used for enhancing pulling low of the output signal of the delay circuit. | 06-11-2009 |
| 20090147594 | VOLTAGE REGULATOR FOR SEMICONDUCTOR MEMORY - A voltage regulator in a semiconductor memory has: a comparing unit including first and second bias current sources, for comparing an output voltage with first and second reference voltages under control of a first signal, the second bias current source being ON under control of a second signal; and a driver active element, coupled to the comparing unit, for outputting the output voltage. Before sensing operations, the output voltage is reset to the second reference voltage. During the sensing operations, the output voltage is maintained at the first reference voltage and the second signal is asserted for turning ON the second bias current source for raising speed of the comparing unit. After the sensing operations, the output voltage is reset to the second reference voltage. | 06-11-2009 |
| 20110188322 | MEMORY DEVICE WITH DATA PATHS FOR OUTPUTTING COMPRESSED DATA - A memory device is provided. The memory device includes a plurality of memory array banks, a bus, a data buffer, and four data paths. The data buffer provides data from the memory array banks to an external node. The first data path includes a first compression module for compressing the data from the memory array banks to the bus. The second data path transmits the data from the memory array banks to the bus. The third data path includes a second compression module for compressing data from the bus to the data buffer. The fourth data path transmits the data from the bus to the data buffer. | 08-04-2011 |
| 20110211398 | MEMORY DEVICE AND ASSOCIATED MAIN WORD LINE AND WORD LINE DRIVING CIRCUIT - A main word line driving circuit for driving word lines in a memory device comprises first and second level shifting units and an inverting unit. The first level shifting unit is configured to convert a decode signal into a first operative signal, and the second level shifting unit is configured to convert the decode signal into a second operative signal. The inverting unit is configured to receive the first and second operative signals. A supply voltage of the first level shifting unit is selectively switched to a first bias voltage when the plurality of word lines are selected or partially selected and switched the output voltage to a second bias voltage when the plurality of word lines are deselected. | 09-01-2011 |
| 20110211407 | SEMICONDUCTOR MEMORY DEVICE AND ASSOCIATED LOCAL SENSE AMPLIFIER - A semiconductor memory device comprises a plurality of memory cells, a bit line sense amplifier, a local sense amplifier, and a sense amplifier. The memory cells are connected between a word line and a bit line pair, and the bit line sense amplifier is configured to amplify voltages of data from the bit line pair and then transmits the data to a local data line pair. The local sense amplifier is configured to amplify voltages of the data from the local data line pair and transmit the data to a global data line pair in response to first and second control signals, and the sense amplifier is configured to amplify the voltages of the data from the global data line pair and transmit the data to an input/output line pair during a read operation. The local sense amplifier comprises a first read circuit, a second read circuit, and a write circuit, and when the memory device performs the read operation, the data is transmitted from the first read circuit to the write circuit via the second read circuit. | 09-01-2011 |
| 20110211417 | MEMORY DEVICE WITH PSEUDO DOUBLE CLOCK SIGNALS AND THE METHOD USING THE SAME - A method for operating a memory device with pseudo double clock signals comprises the steps of: generating an even clock signal and an odd clock signal, wherein the clock rates of both the even clock signal and the odd clock signal are half that of the input clock signal, and the even clock signal is the inverse signal of the odd clock signal; if the logic level of the even clock signal is | 09-01-2011 |
| 20110227624 | DUTY CYCLE CORRECTION CIRCUIT - A duty cycle correction circuit comprises first and second pulse generators, a clock dividing unit, a detecting unit, and a pulse width control unit. The first pulse generator is configured to generate a first edge of a first pulse signal in synchronization with a first edge of a first clock signal, and the second pulse generator is configured to generate a first edge of a second pulse signal in synchronization with a second edge of the first pulse signal. The clock dividing unit is configured to generate a second clock signal by dividing the frequency of the first clock signal. The detecting unit is configured to generate a detecting signal according to the second clock signal and a time interval between the first edge of the first pulse signal and a second edge of the second pulse signal. In particular, pulse widths of the first and second pulse signals are the same and are adjustable according to a control signal from the pulse width control unit. | 09-22-2011 |
| 20110228620 | TESTING METHOD FOR SEMICONDUCTOR MEMORY DEVICE - A method comprises simultaneously writing a test bit to a plurality of memory cells in the selected sections of a memory array corresponding to column address signals; individually and successively reading output bits from the memory cells in one of the selected sections of a designated row of the memory array corresponding to column address signals and row address signals; and error-checking the output bits with the test bit, wherein the memory array comprises the plurality of memory cells arranged in rows and columns and the memory cells of each row are divided into a plurality of sections. | 09-22-2011 |
| 20110235451 | DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF DRIVING DYNAMIC RANDOM ACCESS MEMORY - A dynamic RAM which includes a first inverter, a second inverter, a sense amplifier, a first pair of switches, a pair of bit lines, and a dynamic RAM cell. The first inverter receives a first driving signal. A power end of the first inverter is coupled to a first voltage source. The second inverter receives a second driving signal output from the first inverter. A power end of the second inverter is coupled to a second voltage source. The sense amplifier senses and amplifies a voltage difference between a first sensing signal and a second sensing signal. A power end of the sense amplifier is coupled to a third voltage source, wherein a voltage value of the second voltage source is between a voltage value of the first voltage source and a voltage value of the third voltage source. | 09-29-2011 |
| 20110239046 | TEST CIRCUIT FOR INPUT/OUTPUT ARRAY AND METHOD AND STORAGE DEVICE THEREOF - The invention provides a test circuit for n input/output arrays. Each of the n input/output arrays has M pairs of input/output. The test circuit includes M write drivers and M comparing circuits. The i | 09-29-2011 |
| 20130021862 | DRAM AND METHOD FOR TESTING THE SAME IN THE WAFER LEVEL BURN-IN TEST MODE - A dynamic random-access memory (DRAM) and a method for testing the DRAM are provided. The DRAM includes a memory cell, a bit line associated with the memory cell, a local buffer, and a bit line sense amplifier (BLSA). The local buffer receives a first power voltage as power supply. The local buffer provides a ground voltage to the bit line when a data signal is de-asserted and provides the first power voltage to the bit line when the data signal is asserted. The BLSA receives a second power voltage as power supply. The BLSA provides the second power voltage to the bit line when the data signal and a wafer level burn-in test signal are both asserted. The second power voltage may be higher than the first power voltage. The wafer level burn-in test signal is asserted when the DRAM is in a wafer level burn-in test mode. | 01-24-2013 |
| 20130049830 | DELAY LOCK LOOP CIRCUIT - The invention provides a delay lock loop circuit (DLL) for generating a locked signal, the DLL circuit includes: a phase detector, a first and a second voltage controlled delay chains, a charge pump and a duty cycle detection pump. The phase detector generates a phase detecting result by detecting a phase difference between the clock signal and the locked signal. The first and the second voltage controlled delay chains generate a first and a second delayed signals by delaying the clock signal according to the first and the second control signals, respectively. The charge pump is used for generating the first and the second control signal according to the phase detecting result. The duty cycle detection pump is used for controlling a voltage level of the second control signal according to the first and the second delayed signals. | 02-28-2013 |
Ming-Chung Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20130057322 | DELAY CIRCUIT AND DELAY STAGE THEREOF - A delay circuit includes at least a delay stage. The delay stage includes an inverting receiver, a capacitive element, an output inverter, and a feedback transistor. The inverting receiver includes a resistive element. An input node of the inverting receiver receives an input signal, and the resistive element is coupled to an output node and an internal node of the inverting receiver. A capacitive element is coupled to the output node of the inverting receiver. An input node of the output inverter is coupled to the output node of the inverting receiver, and an output node of the output inverter outputs an output signal of the delay stage. The feedback transistor is coupled between the output node and the input node of output inverter, such that the feedback transistor compensates a delay time of the inverting receiver as at least one of a process, a supply-voltage, and a temperature varies. | 03-07-2013 |
Ming-Hao Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090096462 | Wafer testing method - A wafer testing method for wafer testing system comprises the steps: loading a wafer and then positioning the wafer relatively to a map file image stored in a map file. The map file is of a first file type. The next step is inspecting the appearance of the wafer. When the user detects defects on the wafer, the positions of the defects are directly recorded in the map file and then the modified map file is saved. The map file can be directly modified when the wafer is in the testing procedure so that the testing time is reduced. Furthermore, the precision of the testing is improved. | 04-16-2009 |
| 20090251815 | Testing system and testing method for inspecting electonic devices - A testing system for inspecting electronic devices includes a first transparent disk, a first image capturing unit disposed under the first transparent disk, a second disk disposed next to the first transparent disk, a guiding unit disposed on adjacent area between the transparent disk and the second disk, and a plurality of second image capturing units disposed around the second disk. A plurality of electronic devices is continuingly supplied onto the first transparent disk and the first image capturing unit is used for capturing the images of the bottom surfaces of the electronic devices. Then, the electronic devices are guided to the second disk via the guiding unit and the second image capturing units are used for capturing the images of other surfaces of the electronic devices. A testing method for electronic devices is further disclosed. | 10-08-2009 |
| 20100290664 | Detection system for detecting appearances of many electronic elements and methods of using the same - A detection system for detecting appearances of many electronic elements includes a rotary module, a feeding module and a detection module. The rotary module has a base structure and a hollow transparent rotary structure disposed on the base structure. The feeding module is disposed beside one side of the hollow transparent rotary structure in order to sequentially guide the electronic elements to the top surface of the hollow transparent rotary structure. The detection module has a plurality of detection units sequentially disposed around the hollow transparent rotary structure. Each detection unit is composed of an image-sensing element for sensing the electronic elements, an image-capturing element for capturing surface images of the electronic elements and a classifying element for classifying the electronic elements. | 11-18-2010 |
Ming-Hung Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120243310 | METHOD OF PROGRAMMING A MULTI-BIT PER CELL NON-VOLATILE MEMORY - A method of programming a multi-bit per cell non-volatile memory is disclosed. In one embodiment, the non-volatile memory is read to obtain a first data of a most-significant-bit (MSB) page on a current word line that succeeds in data reading, wherein the current word line follows a preceding word line on which data reading fails. At least one reference voltage is set. The MSB page on the current word line is secondly programmed with a second data according to the reference voltage, the second data being different from the first data. | 09-27-2012 |
| 20130042051 | PROGRAM METHOD FOR A NON-VOLATILE MEMORY - A program method for a non-volatile memory is disclosed. At least two blocks in the non-volatile memory are configured as 1-bit per cell (1-bpc) blocks. The data of the configured blocks are read and written to a target block in such a way that the data of each said configured block are moved to pages of a same significant bit. In another embodiment, the data of the configured blocks excluding one block are read and written to the excluded block. | 02-14-2013 |
| 20130044542 | METHOD OF SORTING A MULTI-BIT PER CELL NON-VOLATILE MEMORY AND A MULTI-MODE CONFIGURATION METHOD - A method of sorting a multi-bit per cell non-volatile memory includes programming and reading to test an n-bit-per-cell (n-bpc) non-volatile memory, which has a plurality of m-bpc pages, where m is a positive integer from 1 through n. If the m-bpc page fails the test, counting a block associated with the failed m-bpc page to (m-1)-bpc blocks, wherein each said m-bpc page is subjected to at most one time of programming and reading. When m is equal to 1, the 0-bpc block corresponds to a bad block. | 02-21-2013 |
Nien-Jen Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090314366 | FLUIDIC DEVICE - A fluidic device is provided for sealing a proper amount of fluid with a brittle material. By moving an adsorbate through an external adsorption force, the brittle material for pre-sealing is broken, and the fluid flows out to interact with the external environment to generate a pump reaction. In addition, the invention may also be used for storing a liquid reagent in a device for a long time. Thereby, the fluidic device can be made small and portable. | 12-24-2009 |
Pei-Ju Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120281159 | DISPLAY DEVICE AND DISPLAY ARRAY SUBSTRATE - A display device comprises a display array substrate, a common substrate and a display layer. The display array substrate comprises a display region and a periphery region, and at least one chip-bonding area is formed in the periphery region. The display layer is sandwiched between the display array substrate and the common-electrode substrate. A conductive loop is disposed in the periphery region of the display array substrate, and passes through the chip-bonding area. | 11-08-2012 |
Po-Chien Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110273975 | SENSING DEVICE - A sensing device including a base, a pillar, an arm, a sensing element and a driving module is provided. The base has a supporting surface suitable for supporting the object. The pillar is disposed on the supporting surface. The arm has two ends and a pivot portion between the two ends. The pivot position is pivoted to the pillar along an axis substantially parallel to the supporting surface. The sensing element is disposed on the arm and located between an end and the pivot portion. The sensing element is located between the base and the object. The driving module is disposed between the arm and the base. The driving module drives the arm to pivot relatively to the pillar along the axis, and the sensing element moves toward or away from the object as the arm is pivoted. | 11-10-2011 |
Rong-Liang Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090006928 | METHOD AND APPARATUS FOR BURST ERROR DETECTION AND DIGITAL COMMUNICATION DEVICE - A digital communication device is provided for decoding a data stream to generate a receiver output. In the digital communication device, a burst error detector determines burst noise locations corresponding to the data stream according to an error-check equation and accordingly generates a burst error indicator. Thereafter, an inner decoder decodes the data stream to generate an inner decoded stream, comprising an erasure marker for performing an erasure marking process on the inner decoded stream based on the burst error indicator to generate an erasure indicator corresponding to the inner decoded stream. An outer decoder then decodes the inner decoded stream with reference to the erasure indicator to generate the receiver output. | 01-01-2009 |
Sen Yih Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110134280 | SYSTEM AND METHOD FOR CONSTRUCTING HIGH DYNAMIC RANGE IMAGES - A system for constructing a high dynamic range image includes a light generating device, a reflective mirror device, a controller, an image capturing device and an image processing module. The light generating device generates a light beam. The reflective mirror device directs the light beam to an object. The controller generates an intensity controlling signal for controlling the light generating device to modulate an intensity of the light beam in accordance with illuminating parameters, and to generate a direction controlling signal for controlling a reflection direction of the reflective mirror device. The image capturing device obtains an original image of the object or a modulated image of the object. The image processing module analyzes the original image to generate the illuminating parameters, or to construct a high dynamic range image of the object in accordance with the modulated image and the illuminating parameters. | 06-09-2011 |
| 20120154574 | SYSTEM AND METHOD FOR CONSTRUCTING HIGH RESOLUTION IMAGES - A system for constructing high resolution images includes a beam splitter assembly, a light intensity modulator, an image capturing module and an image processing module. The beam splitter assembly is utilized to reflect a light beam generated from a light source generating device and generate a splitting beam. The light intensity modulator is utilized to modulate the intensity of the splitting beam to generate a modulating beam, which includes a predetermined noise. The modulating beam is emitted onto an object to generate a modulating image. The image capturing module is utilized to obtain a plurality of modulating images. The image processing module is utilized to analyze the modulating images to generate a high resolution image. | 06-21-2012 |
Shen-Hsiung Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090185345 | Computer Module Replacement of Digital Signage - The invention provides a computer module replacement design of a digital signage. The digital signage has a main circuit board and a plug-board disposed therein and connected to each other. The plug-board has a plug-card with a plug-slot, and a track disposed on each side thereof. The digital signage is covered up by a back cover so that an opening can be formed at one side edge of the digital signage. The computer module has a frame and a motherboard. The frame has a rail disposed on each side thereof and the motherboard has a slot and a connecting terminal disposed thereon. The slot has an interface socket card. The computer module can be placed into the digital signage through the opening with the rail placed into the track. Therefore, the connecting terminal is connected to the plug-slot and the computer module can be drawn out for maintenance. | 07-23-2009 |
| 20090185347 | HEAT DISSIPATION SYSTEM FOR DIGITAL ELECTRONIC SIGNBOARD - A heat dissipation system for digital electronic signboard includes a first heat dissipation subsystem disposed in a main circuit board area of a digital electronic signboard, and a second heat dissipation subsystem disposed in a computer mainboard area of the digital electronic signboard. The main circuit board area has a plurality of heat dissipation fans disposed therein, wherein one heat dissipation fan is disposed at a side of the main circuit board area, while another heat dissipation fan is disposed at a side of a power supply and can be externally connected to an air guide pipe. The computer mainboard area can also have a plurality of heat dissipation fans disposed therein, wherein one heat dissipation fan is disposed at a side of the computer mainboard, while another heat dissipation fan is disposed on the top of a microprocessor of the computer mainboard. | 07-23-2009 |
Shih-Wen Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080283981 | Chip-On-Lead and Lead-On-Chip Stacked Structure - A chip-stacked package structure comprises a lead frame, a first chip, and a second chip. The led frame is composed of a plurality of inner leads and a plurality of outer leads. The plurality of inner leads comprises a plurality of first inner leads in parallel and a plurality of second inner leads in parallel, wherein the ends of first inner leads and the ends of second inner leads are arranged in rows facing each other at a distance. The active surface of first chip is fixedly connected to the lower surface of first inner leads and second inner leads via a first adhesive layer. A plurality of metal pads is provided near the central area of the active surface of first chip and is exposed. A second adhesive layer is formed on the back surface of second chip for fixedly connecting the back surface of second chip and the upper surface of first inner leads and second inner leads. The gap formed by the thickness of second adhesive layer prevents the bonding wires connecting the first chip from contacting the back surface of second chip. | 11-20-2008 |
Ta-Hsin Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090236270 | WATER PURIFICATION SYSTEM - A water purification system performs a water purification process through physical sterilization, and at least includes a compression device and a decompression device. Water is converted into a high-pressure liquid through the compression device, and then is converted into a high-speed fluid by controlling the cross-sectional area of a spout of the decompression device, thus generating physical effects such as pressure drop and shear stress, so as to damage cell walls of bacteria in the liquid to die-off the bacteria. Therefore, purified water is obtained. | 09-24-2009 |
| 20120251035 | CIRCULAR PHOTONIC CRYSTAL STRUCTURE, LIGHT EMITTING DIODE DEVICE AND PHOTOELECTRIC CONVERSION DEVICE - A method applying a circular photonic crystal structure to improve optical properties of a photoelectric conversion device such as a light emitting diode device, an organic light emitting diode device or a solar cell is provided, wherein the circular photonic crystal structure is configured on a junction surface between two different mediums where passes a light emitted or received by the photoelectric conversion device. The circular photonic crystal structure provides isotropic photonic band gap which conduces high light extraction efficiency. | 10-04-2012 |
| 20120315724 | METHOD AND APPARATUS FOR DEPOSITION OF SELENIUM THIN-FILM AND PLASMA HEAD THEREOF - A method for deposition of a selenium thin-film includes the following steps. First, a plasma head is provided. Then, a substrate is supported in an atmospheric pressure. Next, a solid-state selenium source is dissociated by the plasma head to deposit the selenium thin-film on the substrate. The plasma head includes a chamber, a housing and the solid-state selenium source. Plasma is produced in the chamber. The chamber is surrounded by the housing. The solid-state selenium source is supported by the housing. | 12-13-2012 |
Tsung-Hsien Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100238683 | FLEXIBLE LIGHT-EMITTING APPARATUS - A flexible light-emitting apparatus including a side light-emitting flexible light guide rod, two light emitting diodes, and two lenses is provided. The side light-emitting flexible light guide rod has a first end, a second end opposite to the first end, and a light-emitting surface connecting the first and the second ends. The LEDs are respectively disposed beside the first end and the second end and adapted for emitting light beams toward the side light-emitting flexible light guide rod, respectively. One of the lenses is located between the first end and the LED disposed beside the first end, and the other lens is located between the second end and the LED disposed beside the second end. Each of the light beams enters the side light-emitting flexible light guide rod through the corresponding lens and is transmitted to the outside of the side light-emitting flexible light guide rod through the light-emitting surface. | 09-23-2010 |
Tsung-Yi Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120141937 | Photosensitive Composition and Photoresist - A photosensitive composition and a photoresist are provided. The photoresist is formed by compounding a photosensitive composition. The photosensitive composition comprises a binder agent, a photomonomer and a photoinitiator. The binder agent is formed by polymerizing a binder composition. The binder composition comprises a lactic oligomer. The photomonomer has an amount of about 25-95 parts by weight relative to 100 parts by weight of a solid content of the binder agent. The photo initiator has an amount of about 0.5-15 parts by weight relative to 100 parts by weight of the solid content of the binder agent. | 06-07-2012 |
Tze-Chin Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090054738 | SYSTEM AND METHOD FOR PHYSIOLOGICAL ANALYSIS AND FEEDBACK APPLICATION THEREOF - A system for analyzing physiological information and providing feedback is provided. An interface receives time information recording a time point, physiological information of a first user measured at the time point, and a purpose setting determined by the first user. A processor determines a physiological status according to the time information, the physiological information and a physiological information history, selects one of service providers having service attributes conforming to purpose setting and the physiological status according to the purpose setting and the physiological status, and sends service information corresponding to the selected service provider to the first user. | 02-26-2009 |
Wen-Chiang Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100110636 | Insulating and Dissipating Heat Structure of an Electronic Part - An insulating and dissipating heat structure of an electronic part includes an electronic component, a heat sink attached to one surface of the electronic component, a housing having a first notch for coupling with the heat sink, and fluid filled in the housing for cooling. The housing is made of an insulating material. The heat sink, the fluid, and the housing of the present invention are able to lower the temperate and dissipate heat. Particularly, the housing has the character of insulation to meet the safety requirements of high power electronic parts, without concerning about electric conduction and leakage. | 05-06-2010 |
| 20120250333 | Insulating and Dissipating Heat Structure of an Electronic Part - An insulating and dissipating heat structure of an electronic part includes an electronic component, a heat sink attached to one surface of the electronic component, a housing having a first notch for coupling with the heat sink, and fluid filled in the housing for cooling. The housing is made of an insulating material. The heat sink, the fluid, and the housing of the present invention are able to lower the temperate and dissipate heat. Particularly, the housing has the character of insulation to meet the safety requirements of high power electronic parts, without concerning about electric conduction and leakage. | 10-04-2012 |
Wu-Ching Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110108797 | SINGLE CHIP TYPE WHITE LED DEVICE - A single chip type white light LED device includes a first semiconductor layer of a first doping type, a ZnMnSeTe (Zinc Manganese Selenium Tellurium) red light quantum well, a first barrier layer disposed on the ZnMnSeTe red light quantum well, a green light emitting layer including green light quantum dots disposed on the first barrier layer, a second barrier layer disposed on the green light emitting layer, a blue light emitting layer including blue light quantum dots disposed on the second barrier layer, a third barrier layer disposed on the blue light emitting layer, and a second semiconductor layer disposed on the third barrier layer. | 05-12-2011 |
Yao-Tang Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080205504 | DECISION FEEDBACK EQUALIZERS AND EQUALIZING METHODS THEREOF - Decision feedback equalizers and related equalizing method are provided. One proposed decision feedback equalizer includes: a feed-forward filter for filtering an incoming signal to generate a filtered signal; a feedback filter for generating a feedback signal according to a decision signal; an operating device, coupled to the feed-forward filter and the feedback filter, for generating an output signal according to the filtered signal and the feedback signal; a decision device, coupled to the operating device and the feedback filter, for generating the decision signal according to the output signal; and an updating device coupled to the feedback filter for constraining coefficients of predetermined taps of the feedback filter while updating the tap coefficients of the feedback filter; wherein each predetermined tap of the feedback filter corresponds to a tap of the feed-forward filter. | 08-28-2008 |
Yen-I Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100123383 | DUAL-PURPOSE LIGHT-PENETRATING AND LIGHT-EMITTING DEVICE AND LIGHT-PENETRATIVE ILLUMINATING STRUCTURE - A dual-purpose light-penetrating and light-emitting device is provided. The dual-purpose light-penetrating and light-emitting device includes a first transparent substrate, a spacing sidewall, a second transparent substrate, and a light-penetrative illuminating structure. The spacing sidewall is disposed between the first transparent substrate and the second transparent substrate for configuring a hermetic space. The light-penetrative illuminating structure includes a cathode structure, an anode structure, a low pressure gas layer, and a patterned fluorescent layer. The low pressure gas layer is accommodated in the hermetic space. The cathode structure and the anode structure are oppositely disposed on the first transparent substrate and the second transparent substrate, respectively. The patterned fluorescent layer is positioned between the cathode structure and the anode structure, for allowing an ambient natural light penetrating therethrough. | 05-20-2010 |
| 20100141112 | ELECTRON EMISSION DEVICE AND METHOD OF PACKAGING THE SAME - An electron emission device including a first substrate, a second substrate, a gas, a sealant, and a phosphor layer is provided. The first substrate has a cathode thereon, and the cathode has a patterned profile. The second substrate is opposite to the first substrate and has an anode thereon. The sealant is disposed at edges of the first substrate and the second substrate to assemble the first and second substrates. The gas is disposed between the cathode and the anode and configured to induce a plurality of electrons from the cathode, wherein the pressure of the gas is between 10 torr and 10− | 06-10-2010 |
| 20100147689 | METHOD FOR MODIFYING SURFACE OF ALUMINUM OXIDE AND ELECTROOSMOSIS PUMP AND ELECTRIC POWER GENERATOR USING MODIFIED ALUMINUM OXIDE MEMBRANE - The invention provides a method for modifying a surface of aluminum oxide. Aluminum oxide is contacted with a hydrogen peroxide aqueous solution having 5-70 volume % of hydrogen peroxide for 20 minutes to 3 hours. The invention also provides an electroosmosis pump and electric power generator having a porous aluminum oxide membrane modified by the above method. | 06-17-2010 |
| 20100148657 | Plane light source - A plane light source is provided. The plane light source includes an anode layer, a cathode layer, a discharging gas, and at least one fluorescent layer. The discharging gas is between the anode layer and the cathode layer. The fluorescent layer is disposed on the anode layer and located between the anode layer and the cathode layer. In the plane light source, electrons is activated by discharge of the discharging gas and emitted from the cathode layer. The fluorescent layer is adapted for emitting a light when being bombarded by the electrons. | 06-17-2010 |
| 20110183576 | METHOD OF PACKAGING ELECTRON EMISSION DEVICE - An electron emission device including a first substrate, a second substrate, a gas, a sealant, and a phosphor layer is provided. The first substrate has a cathode thereon, and the cathode has a patterned profile. The second substrate is opposite to the first substrate and has an anode thereon. The sealant is disposed at edges of the first substrate and the second substrate to assemble the first and second substrates. The gas is disposed between the cathode and the anode and configured to induce a plurality of electrons from the cathode, wherein the pressure of the gas is between 10 torr and 10 | 07-28-2011 |
| 20110227498 | 3-DIMENSION FACET LIGHT-EMITTING SOURCE DEVICE AND STEREOSCOPIC LIGHT-EMITTING SOURCE DEVICE - A 3-dimension facet light-emitting source device including a transparent container, an anode plate, a cathode plate, a plurality of transparent plates and a low-pressure gas layer is provided. The transparent container has a sealed space. The transparent plates are disposed between the anode plate and the cathode plate, and have a fluorescent layer thereon respectively. The lower pressure gas layer is filled in the sealed space to induce electrons emitting from the cathode plate, and the electrons fly in a direction parallel to the transparent plates and hit each fluorescent layer to emit light, so as to form a set of 3-dimension facet patterns. | 09-22-2011 |
Yi-Chun Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080309219 | PHOSPHORS AND LIGHTING APPARATUS USING THE SAME - A phosphor has a chemical formula of: A(B | 12-18-2008 |
Yi-Heng Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20130050596 | AUTO-STEREOSCOPIC DISPLAY AND METHOD FOR FABRICATING THE SAME - An auto-stereoscopic display suitable for being viewed by a viewer is provided. The auto-stereoscopic display includes a display panel and an adjustable parallax barrier module. The adjustable parallax barrier module is disposed between the display panel and the viewer. The adjustable parallax barrier module includes a plurality of parallax barrier stacked upon each other. The distances between the display panel and each of the parallax barrier are different. One of the parallax barriers is selected and enabled based on the distance between the viewer and the display panel. Besides, a method of fabricating the auto-stereoscopic display is also provided. | 02-28-2013 |
Yi-Teh Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120298982 | High-Gain Complementary Inverter with Ambipolar Thin Film Transistors and Fabrication Thereof - The present invention relates to a high gain complementary inverter with ambipolar thin film transistors and fabrication thereof, comprising: a gate layer, a silica layer, a first active layer, a first source, a first drain, a second active layer, a second source and a second drain for fabrication cost and complexity reduction. | 11-29-2012 |
Yu-Kai Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20130027232 | ANALOG-TO-DIGITAL CONVERTERS AND ANALOG-TO-DIGITAL CONVERSION METHODS - An analog-to-digital converter is provided and comprises a most significant bit (MSB) conversion module, a successive approximation register analog-to-digital converter (SAR ADC) module, and an operation module. The MSB conversion module receives an analog signal to be converted, and converts the analog signal to an MSB with M bits, and obtains a redundancy signal. The SAR ADC module is coupled to the MSB conversion module. The SAR ADC receives the redundancy signal and processes the redundancy signal to be a least significant bit (LSB) with N bits. The operation module is coupled to the MSB conversion module and the SAR ADC module. The operation module receives the MSB with the M bits and the LSB with the N bits and generates a first digital signal with (M+N) bits. Each of M and N is positive, and (M+N) is a positive integer. | 01-31-2013 |
| 20130033391 | MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS AND PIPELINE ANALOG-TO-DIGITAL CONVERTER USING THE SAME - A multiplying digital-to-analog converter (MDAC) is provided. The MDAC includes a sub DAC decoding circuit, a capacitor-switch circuit, and an operation amplifier circuit. The capacitor-switch circuit includes at least two sampling capacitor sets which are coupled in parallel. The number of sampling capacitors in one of the sampling capacitor sets is larger than or equal to two. Each sampling capacitor set is coupled to an analog-signal input quantity through a sampling switch and to a corresponding output terminal of the sub DAC decoding circuit through a decoding switch. The sub DAC decoding circuit decodes a digital quantity and outputs a corresponding analog signal at each output terminal, such that the corresponding analog signals are applied to the respective sampling capacitor sets through the decoding switches and summed by the respective sampling capacitor sets to obtain an analog-signal quantity corresponding to the digital quantity. | 02-07-2013 |
| 20130038483 | ANALOG-TO-DIGITAL CONVERTERS AND PIPELINE ANALOG-TO-DIGITAL CONVERTERS - An analog-to-digital converter is provided. The analog-to-digital converter includes a sampling-voltage providing circuit, a first comparison circuit, a second comparison circuit, and an encoder circuit. The sampling-voltage providing circuit provides a group of first comparison voltages and a group of second comparison voltages. The first comparison circuit performs a first comparison operation to an analog-signal input quantity according to the group of first comparison voltages to generate a first comparison digital quantity. The second comparison circuit selects second comparison voltages among the group of second comparison voltages according to the first comparison digital quantity and performs a second comparison operation to the analog-signal input quantity according to the selected second comparison voltages to generate a second comparison digital quantity. The encoder circuit encodes the first comparison digital quantity and the second comparison digital quantity and generates a digital quantity corresponding to the analog-signal input quantity. | 02-14-2013 |
Yunk-Chia Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100156557 | PHASE SHIFTER - A phase shifter includes a substrate, an input part, a plurality of first transmission lines, a plurality of second transmission lines, a coupling part, a controller, and a plurality of output parts. When a signal is fed in a first transmission line, the fed signal is distributed to a corresponding second transmission line via the first transmission line, and an area of the second transmission line shielded by the coupling part is changed by rotating the coupling part through the controller, so as to shift a phase of the signal transmitted by the second transmission line. | 06-24-2010 |
Yun-Lung Chou, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090269072 | METHODS FOR ALLOCATING TRANSMISSION BANDWIDTHS OF A NETWORK - Methods for allocating transmission bandwidths of a network are adapted to a network including an office terminal and peripheral terminals. The peripheral terminals communicate with the office terminal by time division multiplexing during a sequence of transmitting cycles. The method includes receiving requested bandwidths from uploading messages delivered from the peripheral terminals, arranging an uploading order of the peripheral terminals based on the uploading messages to obtain a transmitting sequence, adjusting the uploading order of each of the peripheral terminals in the transmitting sequence based on a size of the requested bandwidth to obtain a modified transmitting sequence, and arranging a modified uploading order of the peripheral terminals based on the modified transmitting sequence. Therefore, the transmission bandwidth allocation is fairer, and delay is reduced. Upstream order of each terminal is transferred based on its requested bandwidth, thereby effectively reducing the average delay. | 10-29-2009 |