Choong-Ho Lee
Choong-Ho Lee, Kyungki-Do KR
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20090127633 | NON-VOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - In one embodiment, a semiconductor memory device includes a substrate having first and second active regions. The first active region includes a first source and drain regions and the second active region includes a second source and drain regions. A first interlayer dielectric is located over the substrate. A first conductive structure extends through the first interlayer dielectric. A first bit line is on the first interlayer dielectric. A second interlayer dielectric is on the first interlayer dielectric. A contact hole extends through the second and first interlayer dielectrics. The device includes a second conductive structure within the contact hole and extending through the first and second interlayer dielectrics. A second bit line is on the second interlayer dielectric. A width of the contact hole at a bottom of the second interlayer dielectric is less than or substantially equal to a width at a top of the second interlayer dielectric. | 05-21-2009 |
20110095377 | SEMICONDUCTOR MEMORY DEVICES - In some embodiments, a semiconductor memory device includes a substrate that includes a cell array region and a peripheral circuit region. The semiconductor memory device further includes a device isolation pattern on the substrate. The device isolation pattern defines a first active region and a second active region within the cell array region and a third active region in the peripheral circuit region. The semiconductor memory device further includes a first common source region, a plurality of first source/drain regions, and a first drain region in the first active region. The semiconductor memory device further includes a second common source region, a plurality of second source/drain regions, and a second drain region in the second active region. The semiconductor memory device further includes a third source/drain region in the third active region. The semiconductor memory device further includes a common source line contacting the first and second common source regions. | 04-28-2011 |
Choong-Ho Lee, Giheung-Gu KR
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20110076389 | DEPOSITION SOURCE AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DEVICE - A deposition source which improves deposition characteristics and uniformity of a deposited film, and a method of manufacturing an organic light-emitting device. The deposition source includes a heat source, a heat transfer plate arranged on the heat source and adapted to receive heat generated by and transferred from the heat source and a planarization layer arranged on the heat transfer plate, the heat source to supply more heat per unit area to outer portions of the heat transfer plate that surrounds a central portion of the heat transfer plate than to the central portion of the heat transfer plate. | 03-31-2011 |
Choong-Ho Lee, Gyeonggi-Dol KR
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20090315094 | Nonvolatile Memory Device - Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string. | 12-24-2009 |
20110310665 | Nonvolatile Memory Device - Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string. | 12-22-2011 |
Choong-Ho Lee, Euiwang-Si KR
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20090273655 | INK RESERVOIR FOR INKJET PRINT SYSTEM - A replaceable ink reservoir adapted to an inkjet print system is provided. Since the inkjet print system of the conventional arts drives an air pump to inject air into the ink reservoir to discharge the ink stored in the ink storage pack to a printer cartridge, serious noise may be generated when the air pump is driven. In addition, in order to discharge the ink through the injection of the air, the ink reservoir should be one integrated body having a hermetically sealed structure, therefore, a user cannot visually check an ink storage level in the ink storage pack from the exterior of the ink reservoir. Further, since a nozzle connecting pipe is always connected to an ink outlet port connected to a front end of the ink storage pack, it is difficult to uniformly maintain discharge pressure of the ink, thereby causing an error image to be formed on a recording medium. Therefore, the present invention provides an ink reservoir for an inkjet print system, which is visually checkable an ink discharge amount in an ink storage pack and refilling the ink in the ink storage pack received in the ink reservoir by constituting the ink reservoir using transparent assemblies, discharges the ink in the ink storage pack received in the ink reservoir using inherent expansion of an expansion member, and includes a dual safety device and a dual cover installed at front ends of the ink storage pack and the ink outlet port to block ink discharged from the ink storage pack when a print operation is completed, thereby preventing unnecessary consumption of the ink. | 11-05-2009 |
Choong-Ho Lee, Seognam-Si KR
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20090267137 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING NOTCHED GATE MOSFET - Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized bits, and transistors having structures optimized to satisfy different requirements depending upon functions of the transistors can be formed on a peripheral circuit area which is the residual area of the semiconductor substrate. In this method, a cell transistor is formed on the cell array area. The cell transistor includes a notch gate structure, a first channel region formed on a semiconductor substrate under the notch gate structure, a source region and a drain region formed on both sides of the first channel region, a first gate insulation film formed between the first channel region and the notch gate structure, and a memory layer locally formed on areas adjacent to the source and drain regions between the first channel region and the notch gate structure. At the same time that the cell transistor is formed, a plurality of peripheral circuit transistors including at least one transistor having a different structure from the cell transistor are formed on the peripheral circuit area. | 10-29-2009 |
Choong-Ho Lee, Suwon-Si KR
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20090233513 | FRIT SEALING SYSTEM - A frit sealing system for combining a first substrate and a second substrate using frit comprises a laser generating a laser beam, and a homogenizer normalizing the intensity of the laser beam within a cross section of the laser beam in the transverse direction. The frit sealing system further comprises a support apparatus configured to hold a first and a second substrate with frit interposed between them, wherein the frit is configured to be cured by heat generated from the laser beam and thereby solidifying and binding the first and the second substrates. | 09-17-2009 |
20090233514 | Frit sealing system and method of manufacturing organic light emitting display device - A frit sealing system and a method of manufacturing an organic light emitting display device by using the frit sealing system, and more particularly, a frit sealing system and a method of manufacturing an organic light emitting display device by using the frit sealing system, which includes a pressure member so as to physically pressurize a first substrate and a second substrate, thereby increasing adhesion of a frit when the first substrate and the second substrate are adhered to each other by using the frit. The frit sealing system, adhering the first substrate and the second substrate by using the frit, includes: a bed member on which the first substrate is placed; a laser irradiation member irradiating a laser to the frit between the first substrate and the second substrate; and a pressure member disposed on an upper part of the first substrate and the second substrate irradiated with the laser and adhered, thereby pressurizing the first substrate and the second substrate irradiated with the laser and adhered. | 09-17-2009 |
20090237324 | Dual display module and display apparatus having the same - A dual display module having a first display panel and a second display panel, the dual display module including a bezel arranged between the first display panel and the second display panel, and having a penetration area between the first display panel and the second display panel; and a supporting member arranged between the bezel and the second display panel and supporting the second display panel, the supporting member having at least one protrusion unit that protrudes through the penetration area to face the first display panel. | 09-24-2009 |
Choong-Ho Lee, Yongi-Si KR
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20130221447 | FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME - Provided are field effect transistors and methods of fabricating the same. The transistor may include a substrate with an active pattern, the active pattern having a top surface and two sidewalls, a gate electrode proximal to the top surface and the sidewalls of the active pattern and crossing the active pattern, a gate spacer covering a sidewall of the gate electrode, a gate dielectric pattern at a bottom surface of the gate electrode, a source electrode on the active pattern at one side of the gate electrode, a drain electrode on the active pattern at another side of the gate electrode, and silicide patterns on surfaces of the source and drain electrodes, respectively. The gate dielectric pattern includes at least one high-k layer and the gate spacer has a dielectric constant that is smaller than that of the gate dielectric pattern. | 08-29-2013 |
Choong-Ho Lee, Sungnam-Si KR
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20150228796 | FIN FET AND METHOD OF FABRICATING SAME - A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode. | 08-13-2015 |