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| 20110003421 | METHOD OF FORMING MONOLITHIC CMOS-MEMS HYBRID INTEGRATED, PACKAGED STRUCTURES - A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip; applying a second insulating layer overlying the metallization layer on the at least one chip; applying at least one interfacial layer; applying at least one rigid substrate overlying the interfacial layer; and applying at least one secondary protective layer overlying the rigid substrate. | 01-06-2011 |
| 20110003422 | METHOD OF FORMING MONOLITHIC CMOS-MEMS HYBRID INTEGRATED, PACKAGED STRUCTURES - A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip; applying a second insulating layer overlying the metallization layer on the at least one chip; applying at least one interfacial layer; applying at least one rigid substrate overlying the interfacial layer; and applying at least one secondary protective layer overlying the rigid substrate. | 01-06-2011 |
| 20110027941 | METHOD OF FORMING MONOLITHIC CMOS-MEMS HYBRID INTEGRATED, PACKAGED STRUCTURES - A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing a semiconductor substrate with pre-fabricated cmos circuits on the front side and a polished back-side with through substrate conductive vias; forming at least one opening in the polished backside of the semiconductor substrate by appropriately protecting the front-side; applying at least one filler material in the at least one opening on the semiconductor substrate; positioning at least one prefabricated mems, nems or cmos chip on the filler material, the chip including a front face and a bare back face with the prefabricated mems/nems chips containing mechanical and dielectric layers; applying at least one planarization layer overlying the substrate, filler material and the chip; forming at least one via opening on a portion of the planarization layer interfacing pads on the chip and the through substrate conductive vias; applying at least one metallization layer overlying the planarization layer on the substrate and the chip connecting the through substrate conductive vias to the at least one chip; applying at least one second insulating layer overlying the metallization layer; performing at least one micro/nano fabrication etching step to release the mechanical layer on the prefabricated mems/nems chips; positioning protective cap to package the integrated device over the mems/nems device area on the pre-fabricated chips. | 02-03-2011 |
| 20110054579 | FLEXIBLE PENETRATING ELECTRODES FOR NEURONAL STIMULATION AND RECORDING AND METHOD OF MANUFACTURING SAME - A flexible penetrating array for neuronal applications includes an insulating layer. A conductive layer is formed on the insulating layer. A flexible polymer substrate is formed on the conductive layer; the polymer substrate includes defined penetrating electrodes. A first metallization layer is formed on the polymer substrate. A second flexible polymer layer is formed on the first metallization layer. A second metallization layer is formed on the second flexible polymer layer. A third flexible polymer layer is formed on the second metallization layer. The third flexible polymer layer is patterned to expose the second metallization layer that is integrated with the out of plane conductive layer and first metallization layer. Also disclosed is a method of forming the array. | 03-03-2011 |
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| 20090075620 | LOCAL OSCILLATOR BUFFER AND MIXER HAVING ADJUSTABLE SIZE - Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an exemplary embodiment, LO buffer and/or mixer size may be increased when a receiver or transmitter operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver or transmitter operates in a low gain mode. In an exemplary embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific exemplary embodiments of LO buffers and mixers having adjustable size are disclosed. | 03-19-2009 |
| 20090111414 | LOCAL OSCILLATOR BUFFER AND MIXER HAVING ADJUSTABLE SIZE - Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an embodiment, LO buffer and/or mixer size may be increased when a receiver operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver operates in a low gain mode. In an embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific embodiments of LO buffers and mixers having adjustable size are disclosed. | 04-30-2009 |
| 20090154595 | I-Q MISMATCH CALIBRATION AND METHOD - Techniques are provided for reducing mismatch between the in-phase (I) and quadrature (Q) channels of a communications transmitter or receiver. In an exemplary embodiment, separate voltages are applied to bias the gates or bulks of the transistors in a mixer of the I channel versus a mixer of the Q channel. In another exemplary embodiment, separate voltages are applied to bias the common-mode reference voltage of a transimpedance amplifier associated with each channel. Techniques are further provided for deriving bias voltages to minimize a measured residual sideband in a received or transmitted signal, or to optimize other parameters of the received or transmitted signal. Techniques for generating separate bias voltages using a bidirectional and unidirectional current digital-to-analog converter (DAC) are also disclosed. | 06-18-2009 |
| 20100321137 | PROGRAMMABLE VARACTOR AND METHODS OF OPERATION THEREOF - Exemplary embodiments are directed to a programmable varactor device. A varactor device may include an input device configured to receive a tuning voltage and generate a bias voltage at least partially dependent on the tuning voltage. The varactor device may also include a varactor pair coupled to the input device and having a first variable capacitor and a second variable capacitor, wherein each of the first variable capacitor and a second variable capacitor are configured for operable coupling to each of the bias voltage and the tuning voltage. | 12-23-2010 |
| 20110001539 | MIXER-TRANSCONDUCTANCE INTERFACE - Techniques for providing an efficient interface between a mixer block and a transconductance (Gm) block. In an exemplary embodiment, the output currents of at least two unit cells of the transconductance block are conductively coupled together, and coupled to the mixer block using a single conductive path. For a differential signal, the conductive path may include two conductive leads. Within the mixer block, the single conductive path may be fanned out to at least two unit cells of the mixer block. At least one Gm unit cell may be selectively enabled or disabled to control the gain setting of the mixer-transconductance block. The techniques may further be applied to transceiver architectures supporting in-phase and quadrature mixing, as well as multi-mode and/or multi-band operation. | 01-06-2011 |
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| 20080238370 | BATTERY PACK FOR CORDLESS POWER TOOLS - A battery pack which includes a battery pack electronic control circuit adapted to control an attached power tool and/or an attached charger. The battery pack includes additional protection circuits, methodologies and devices to protect against fault conditions within the pack, as the pack is operatively attached to and providing power to the power tool, and/or as the pack is operatively attached to and being charged by the charger. | 10-02-2008 |
| 20080315834 | Battery pack chargers and charging method - A method of charging a battery pack is provided. The method includes: electronically connecting a battery pack to a charger; detecting information regarding the battery pack; determining an appropriate charging regime based on the detected information; and applying the charging regime to the battery pack. A battery charger may also provided. The battery charger includes: a first terminal for connecting to a battery pack; a second terminal for connecting to a battery pack, a microprocessor operatively connected to the terminals and configured to receive a signal from at least one terminal regarding a battery pack connected to the terminal and control the charger to select and apply a charging regime to the battery pack according to the signal. | 12-25-2008 |
| 20100213900 | BATTERY PACK FOR CORDLESS POWER TOOLS - A battery pack which includes a battery pack electronic control circuit adapted to control an attached power tool and/or an attached charger. The battery pack includes additional protection circuits, methodologies and devices to protect against fault conditions within the pack, as the pack is operatively attached to and providing power to the power tool, and/or as they pack is operatively attached to and being charged by the charger. | 08-26-2010 |
| 20110163701 | Battery Pack for Cordless Power Tools - A battery pack which includes a battery pack electronic control circuit adapted to control an attached power tool and/or an attached charger. The battery pack includes additional protection circuits, methodologies and devices to protect against fault conditions within the pack, as the pack is operatively attached to and providing power to the power tool, and/or as the pack is operatively attached to and being charged by the charger. | 07-07-2011 |
