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Choi, TX
Alexander Choi, Houston, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090195217 | PROVIDING POWER BASED ON STATE OF CHARGE - A modular and scalable power source can be used to supplement an existing source of power. In one embodiment, a DC source can be used to maintain a power source of a host system in a specific state in order to cause a desired behavior. | 08-06-2009 |
| 20090206798 | POWER SOURCE WITH TEMPERATURE SENSING - A modular and scalable power source can be used to supplement and/or replace existing sources of power. In some embodiments, a DC source can be used to charge a battery in a host system, provide power as a back-up system, or be a primary source of power. The power source includes a set of battery units and one or more circuits that provide an alternative signal path around the battery units if the battery units are at a particular charge level. Temperature sensors are used to turn off or otherwise adjust the alternative signal paths if the temperatures of the alternative signal paths become too high. | 08-20-2009 |
Arnold Choi, Houston, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100025548 | Pipe Support Assembly - A pipe support assembly for supporting one or more pipes. According to an embodiment, the pipe support assembly comprises a main member having a saddle for holding a first pipe, a pipe holder attached to the main member and configured for holding a second pipe, and the main member includes an exterior surface for receiving a support strap for affixing to the structure. According to an embodiment, the first pipe comprises an insulated pipe with an outer insulation layer and the second pipe comprises an uninsulated pipe. According to another embodiment, the pipe support assembly includes a bottom mount for mounting the pipe support assembly to a structure. According to an embodiment, the mount comprises a bracket. According to another aspect, the mount comprises a base that is fastened to a structure. | 02-04-2010 |
Byung J. Choi, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080199816 | Method of Automatic Fluid Dispensing for Imprint Lithography Processes - Disclosed herein is an automatic fluid dispensing method and system for dispensing fluid on the surface of a plate-like material, or substrate, including a semiconductor wafer for imprint lithography processes. The dispensing method uses fluid dispenser and a substrate stage that may generate relative lateral motions between a fluid dispenser tip a substrate. Also described herein are methods and devices for creating a planar surface on a substrate using a substantially unpatterned planar template. | 08-21-2008 |
| 20100173033 | Device for Holding a Template for Use in Imprint Lithography - An imprint lithography template may be used to form an imprinted layer in a light curable liquid disposed on a substrate. During use, the template may be disposed within a template holder. The template holder may include a body with an opening configured to receive the template, a support plate, and an actuator system coupled to the body. The actuator system may be configured to alter a physical dimension of the template during use. | 07-08-2010 |
| 20100201042 | Step and Repeat Imprint Lithography Processes - Methods of forming continuous layers on regions of a substrate are described. Generally, an imprint lithography template may contact liquid positioned on the substrate. The liquid may be cured forming a masking layer, and the imprint lithography template separated from the masking layer. Prior to separation, pressurized gas and/or vacuum may be applied between the template and the substrate. Additionally, during separation, pressurized gas and/or vacuum may be applied between the template and the substrate. | 08-12-2010 |
| 20110221095 | Step and Repeat Imprint Lithography Process - The present invention is directed to methods for patterning a substrate by imprint lithography. Imprint lithography is a process in which a liquid is dispensed onto a substrate. A template is brought into contact with the liquid and the liquid is cured. The cured liquid includes an imprint of any patterns formed in the template. In one embodiment, the imprint process is designed to imprint only a portion of the substrate. The remainder of the substrate is imprinted by moving the template to a different portion of the template and repeating the imprint lithography process. | 09-15-2011 |
Byung-Kwon Choi, Katy, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100035867 | Inhibitors of Cyclic Nucleotide Synthesis and Their Use for Therapy of Various Diseases - We disclose a method of inhibiting activity of adenylyl cyclase or guanylyl cyclase in a mammal by administering to the mammal an amount of a composition effective to inhibit the activity, wherein the composition contains at least one compound selected from the group consisting of structural formulae (Ia) and (Ib) and salts thereof, wherein R1 is —H or has the structure —C(═O)R8; R2 is ═O or has the structure —OC(═O)R9; and R3, R4, R5, R6, and R7 are each independently selected from the group consisting of —H, —NO | 02-11-2010 |
Chulchae Choi, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080273830 | SYSTEM, METHOD AND APPARATUS FOR IMPROVED ELECTRICAL-TO-OPTICAL TRANSMITTERS DISPOSED WITHIN PRINTED CIRCUIT BOARDS - The present invention provides a system, method and apparatus for improved electrical-to-optical transmitters ( | 11-06-2008 |
Guibog Choi, Houston, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110265701 | Spar Hull Centerwell Arrangement - A spar hull centerwell arrangement wherein an adjustable buoyancy centerwell device (ABCD) is disposed within the centerwell of the structure. The adjustable buoyancy centerwell device is rigidly connected to the interior walls of the hard tank and defines an adjustable buoyancy centerwell device within the centerwell. The adjustable variable buoyancy unit is a water and airtight buoyancy chamber that allows the interior ballast to be changed as required. This device can also be used as a storage unit for on board fluids and other produced hydrocarbons. | 11-03-2011 |
Gwan S. Choi, College Station, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080276156 | LOW DENSITY PARITY CHECK DECODER FOR REGULAR LDPC CODES - A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message. | 11-06-2008 |
| 20080301521 | LOW DENSITY PARITY CHECK DECODER FOR IRREGULAR LDPC CODES - A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density parity check (“LDPC”) matrix out of order. A decoder embodiment may process the layers of the LDPC matrix out of order and/or perform partial state processing on out of order blocks of the LDPC matrix and/or generate R messages out of order. | 12-04-2008 |
Han-Sun Choi, Houston, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080204759 | METHOD FOR DEMODULATING SIGNALS FROM A DISPERSIVE WHITE LIGHT INTERFEROMETRIC SENSOR AND ITS APPLICATION TO REMOTE OPTICAL SENSING - A method for demodulating signals from a dispersive, white light interferometer includes generating test interferometry spectra from an interferometer forming part of a sensor for various values of interferometer sensor optical path length. The various test spectra are correlated to a measured spectrum from the sensor to generate a correlation function. The sensor optical path length resulting in the correlation function value reaching a maximum is selected as the optical path length | 08-28-2008 |
Hosoon Choi, Belton, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110223138 | Mesenchymal stem cells that express increased amounts of anti-apoptotic proteins - The invention includes a purified population of mesenchymal stromal cells that have been cultured under conditions, such as having been contacted with an apoptotic cell, to express increased levels of at least one anti-apoptotic protein. Such mesenchymal stem cells may be used to treat diseases, disorders, or conditions associated with apoptosis or with unresolved inflammation. | 09-15-2011 |
Jinhan Choi, Frisco, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080233747 | Semiconductor Device Manufactured Using an Improved Plasma Etch Process for a Fully Silicided Gate Flow Process - In one aspect, there us provided a method of manufacturing a semiconductor device that comprises placing an oxide layer over a gate electrode and sidewall spacers located adjacent thereto, placing a protective layer over the oxide layer, conducting a plasma etch to remove portions of the protective layer and the first oxide layer that are located over the gate electrode and expose a surface of the gate electrode, wherein the plasma etch is selective to polysilicon. A soft etch is conducted subsequent to the plasma etch. The soft etch includes an inorganic-based fluorine containing gas and an inert gas, wherein the plasma etch leaves a film on the gate electrode that inhibits silicidation of the gate electrode and wherein the soft etch removes the film. The gate electrode is silicided with a metal subsequent to conducting the soft etch. | 09-25-2008 |
| 20080242072 | PLASMA DRY ETCH PROCESS FOR METAL-CONTAINING GATES - A method of manufacturing a semiconductor device. The method comprises forming a gate stack layer. The gate stack has an insulating layer on a substrate, a metal-containing layer on the insulating layer, a metal nitride barrier layer on the metal-containing layer, and a silicon-containing layer on the metal nitride barrier layer. The method also comprises patterning the gate stack layer. Pattering includes a plasma etch of the metal nitride barrier layer. The plasma etch has a chloride-containing feed gas and a physical etch component. The physical etch component includes a high-mass species having a molecular weight of greater than about 71 gm/mol. | 10-02-2008 |
| 20100167514 | POST METAL GATE VT ADJUST ETCH CLEAN - A method for fabricating a CMOS integrated circuit (IC) includes providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the semiconductor surface followed by forming at least a first metal including layer on the gate dielectric layer. A polysilicon or amorphous silicon layer is formed on the first metal including layer to form an intermediate gate electrode stack. A masking pattern is formed on the intermediate gate electrode stack. The polysilicon or amorphous silicon layer is dry etched using the masking pattern to define a patterned intermediate gate electrode stack over the NMOS or PMOS regions, wherein the dry etching stops on a portion of the first metal comprising layer. The masking pattern is removed using a first post etch clean for stripping the masking pattern. A multi-step solution cleaning sequence is used after the removing step and includes a first wet clean including sulfuric acid and a fluoride, and a second wet clean after the first wet clean including a fluoride. Fabrication of the IC is then completed. | 07-01-2010 |
| 20100167519 | POST HIGH-K DIELECTRIC/METAL GATE CLEAN - A method for fabricating a CMOS integrated circuit (IC) includes the step of providing a substrate having a semiconductor surface. A gate stack including a metal gate electrode on a metal including high-k dielectric layer is formed on the semiconductor surface. Dry etching is used to pattern the gate stack to define a patterned gate electrode stack having exposed sidewalls of the metal gate electrode. The dry etching forms post etch residuals some of which are deposited on the substrate. The substrate including the patterned gate electrode stack is exposed to a solution cleaning sequence including a first clean step including a first acid and a fluoride for removing at least a portion of the post etch residuals, wherein the first clean step has a high selectivity to avoid etching the exposed sidewalls of the metal gate electrode. A second clean after the first clean consists essentially of a fluoride which removes residual high-k material on the semiconductor surface. | 07-01-2010 |
Jinho Choi, Lewisville, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100188871 | SYNCHRONOUS RECTIFIER NETWORK UNIT CIRCUIT AND METHOD - A synchronous rectifier network unit and synchronous rectifying method. The synchronous rectifier network unit includes a first body diode to which a first current flows at a first time when the first current flows to a first coil, and a first transistor which is turned on after the first body diode is conducted, and to which the first current flows, and it rectifies the first current by differently controlling the turn-off time of the first transistor according to the first current. | 07-29-2010 |
Jin Ho Choi, Lewisville, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100213944 | Diagnosis Device, Diagnosis Method, And Lamp Ballast Circuit Using The Same - The present invention relates a diagnosis device for detecting an end of lamp life of a lamp, a diagnosis method, and a lamp ballast circuit using the same. The diagnosis device generates a reference lamp voltage by adding a predetermined reference voltage to a distributed voltage corresponding to a lamp voltage applied to a lamp and generates an integrated lamp voltage by integrating the reference lamp voltage. The diagnosis device compares the integrated lamp voltage with a normal range that an integrated lamp voltage has when the lamp is in a normal state. | 08-26-2010 |
Jinwoo Choi, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080204127 | Method for Ultimate Noise Isolation in High-Speed Digital Systems on Packages and Printed Circuit Boards (PCBS) - Improved noise isolation for high-speed digital systems on packages and printed circuit boards is provided by the use of mixed alternating impedance electromagnetic bandgap (AI-EBG) structures and a power island configured to provide ultimate noise isolation. A power island is surrounded by a plurality of mixed AI-EBG structures to provide a power distribution network. In this structure, the gap around the power island provides excellent isolation from DC to the first cavity resonant frequency which is determined by the size of the structure and dielectric material. One AI-EBG structure provides excellent isolation from the first cavity resonant frequency of around 1.5 GHz to 5 GHz. The other AI-EBG structure provides excellent noise isolation from 5 GHz to 10 GHz. Through use of this novel configuration of AI-EBG structures, a combination effect of the hybrid AI-EBG structure provides excellent isolation far in excess of 10 GHz. The AI-EBG structure is a metallic-dielectric EBG structure that comprises two metal layers separated by a thin dielectric material (similar to power/ground planes in packages and PCBs). However, in the AI-EBG structure, only one of the metal layers has a periodic pattern which is preferably a two-dimensional rectangular lattice with each element consisting of a metal patch with four connecting metal branches. | 08-28-2008 |
| 20090307636 | SOLUTION EFFICIENCY OF GENETIC ALGORITHM APPLICATIONS - A method of optimizing a very large scale integrated circuit design takes a circuit description which includes interconnected circuit components and characteristic variables assigned to the circuit components such as environmental, operational or process parameters, computes a first solution for the characteristic variables using a statistical analysis, and then computes a second solution for the characteristic variables using an evolutionary analysis seeded by the first solution. In the exemplary implementation the statistical analysis is a central composite design (CCD) and the evolutionary analysis is a genetic algorithm. Best case and worst case CCD solutions may be used to seed separate genetic algorithm runs and derive global best case and global worst case solutions. These solutions may be compared for sensitivity analysis. The method thereby provides significant reduction in time-to-solution with accurate simulation results. | 12-10-2009 |
| 20100195756 | REDUCED WIRING REQUIREMENTS WITH SIGNAL SLOPE MANIPULATION - An information handling system device includes a plurality of electronic components; an electric circuit including at least one trace for connecting two or more of the plurality of electronic components and transmitting data between the plurality of electronic components via at least one electric signal; and a substrate including an insulating material for serving as a base for the electric circuit and the plurality of electronic components, wherein the at least one electric signal transmitted between the plurality of electronic components is transmitted utilizing slope manipulation to provide a slope directly proportional to a data value. | 08-05-2010 |
| 20100229131 | SWARM INTELLIGENCE FOR ELECTRICAL DESIGN SPACE MODELING AND OPTIMIZATION - A method, system, and computer program product for exploring and optimizing an electrical design space. A computer receiving a design space assigns a plurality of initial values (random or predetermined) for optimizing the design space. A particle swarm containing a plurality of particles is created and an optimization of the design space is then performed using the assigned initial values. Following completion of optimization, the global best and personal best for each particle are updated. Velocity vectors and position vectors of the design space are then updated before the computer performs the optimization process again. The process loops, continually updating global and personal bests and velocity and position vectors until a termination criteria is reached. Upon reaching the termination criteria, the best fitness of each particle of the swarm is assigned as an optimized design space. In an alternate embodiment, the particle with the worst target fitness may be assigned. | 09-09-2010 |
| 20100294557 | Transmission Cable with Spirally Wrapped Shielding - Embodiments of the invention are directed to transmission cables, and particularly to twinax cables, for transmitting digital data and other information between components in a data processing environment. One embodiment of the invention is directed to an information transmission cable that comprises first and second signal carrying conductors of specified length, each of the signal carrying conductors being disposed to carry information signals and having a longitudinal axis. The embodiment further includes an insulating structure comprising an amount of specified dielectric insulation material, the insulating structure being positioned to surround the first and second signal carrying conductors along their respective lengths, and acting to maintain the first and second signal conductors in spaced apart parallel relationship with each other. A first drain conductor is positioned proximate to the first signal carrying conductor in spaced apart parallel relationship, and is further positioned in a first prespecified relationship with a reference line that intersects the respective longitudinal axes of the first and second signal carrying conductors, and that lies in a plane orthogonal thereto. In similar manner, a second drain conductor is positioned proximate to the second signal carrying conductor in spaced apart parallel relationship, and is further positioned in a second prespecified relationship with the reference line. Shielding material is spirally wrapped around the first and second signaling conductors, the first and second drain conductors and the insulating structure. | 11-25-2010 |
| 20110061898 | REDUCING CROSS-TALK IN HIGH SPEED CERAMIC PACKAGES USING SELECTIVELY-WIDENED MESH - One embodiment of the invention provides a multi-layered ceramic package. The ceramic package includes a signal layer having a plurality of signal lines and a mesh reference layer parallel to the signal layer. The mesh reference layer includes a plurality of intersecting reference lines of varying reference-line width in the plane of the mesh layer. The mesh reference lines may be widened in locations of probable signal cross-talk. Other embodiments of the invention include software for optimizing a ceramic package design by selectively widening mesh lines in regions of probable cross-talk, and systems for designing and manufacturing such a ceramic package. | 03-17-2011 |
| 20110083888 | Noise Coupling Reduction and Impedance Discontinuity Control in High-Speed Ceramic Modules - An improved multi-layered ceramic package comprises: a plurality of signal layers, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; at least one reference mesh layer adjacent to one or more signal layers; and a plurality of via-connected coplanar-type shield (VCS) lines, with a first VCS line extending on a first side of a first signal line within the plurality of signal layers and a second VCS line extending on a second opposing side of the first signal line. Each of the plurality of VCS lines interconnect with and extend past one or more vias that are located along the directional path in which the VCS lines runs. The placement of the VCS lines relative to the signal lines reduces coupling noise and controls impedance discontinuity in the ceramic package. | 04-14-2011 |
| 20110132650 | High-Speed Ceramic Modules with Hybrid Referencing Scheme for Improved Performance and Reduced Cost - A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s)/site(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below (adjacent to) the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises different mesh configurations from among: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas, and the Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines. | 06-09-2011 |
| 20110161055 | SPACE SOLUTION SEARCH - A statistical approach can be used to efficiently supply an initial population that provides a good global description of a design space. The SI based simulation can then find a global best design within a reduced number of simulations. The statistical approach can be utilized to determine a plurality of potential best and worst case designs from a design space. The plurality of potential best and worst case designs from the design space seed or prime a SI based simulation. The best case designs are based on design parameters than can be controlled. The worst case designs are based on design parameters than cannot be controlled due. SI based simulations can then be run on the best case designs with respect to the worst case designs to determine probability of failure of the best case design. | 06-30-2011 |
| 20110222224 | CORELESS MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE - A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers. | 09-15-2011 |
| 20110289463 | ELECTRICAL DESIGN SPACE EXPLORATION - A method for electrical design space exploration includes receiving a template for an electrical design. Design component parameters associated with at least one component in the electrical design are also received. Weighted factors are assigned to design complexity parameters of the electrical design. The parameters of the complexity can include at least one of following: whether the electrical design is known, a number of the design component parameters, a level of interaction among the design component parameters, a time constraint and a memory restriction of a simulation, and whether a statistical analysis or a worst case approach is used to analyze an output of the simulation. A simulation approach for design space exploration of the electrical design is selected based on the weighted factors for the parameters of the complexity of the electrical design. The simulation is performed based on the selected simulation approach. | 11-24-2011 |
Jou-Young Choi, Katy, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110150631 | TORSIONAL DYNAMIC DAMPER FOR A WIND TURBINE AND METHOD OF USING SAME - A wind turbine includes a tower, a nacelle located adjacent a top of the tower, a rotor coupled to the nacelle, and a dynamic vibration damper coupled to the tower and configured to dampen vibrations induced in the tower in a torsional direction while negligibly effecting vibrations induced in the tower in bending directions. The dynamic vibration damper may be tuned to a resonant frequency of the wind turbine in the torsional direction. A method of retrofitting a wind turbine with a vibration damper is also disclosed. | 06-23-2011 |
Kai-Wai Alexander Choi, Houston, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090079390 | RECHARGEABLE BATTERY ARRAY - Rechargeable battery array is described. The rechargeable battery array is constructed from: a battery row | 03-26-2009 |
| 20090243540 | METHODS AND APPARATUS FOR BATTERY CHARGING MANAGEMENT - A method for managing the charging of a battery array | 10-01-2009 |
| 20090278488 | METHOD FOR DISCHARGE BALANCING OF A BATTERY ARRAY - A method for discharge balancing for a battery array including a plurality of partitions of battery cells | 11-12-2009 |
| 20100009264 | HIGH RATE DISCHARGE BATTERY CELL - A high rate discharge battery cell | 01-14-2010 |
Kyungsik Choi, Plano, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20120039314 | METHOD AND APPARATUS OF SUPPORTING WIRELESS FEMTOCELL CLUSTERS - A method of operating a femtocell network cluster is disclosed. One example method of operating the femtocell network cluster may include certain operations, such as, selecting a master femtocell access point among various femtocell access points operating on the femtocell network cluster and updating a master table to include the master femtocell access point in the master table neighbor list. Other operations may include transmitting the master table to each of the femtocell access points informing them of the identity of the master femtocell access point. The tables may be maintained by all of the femtocell access points operating on the network. | 02-16-2012 |
Myoung Choi, Arlington, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100016961 | Extended Depth of Focus (EDOF) Lens to Increase Pseudo-Accommodation by Utilizing Pupil Dynamics - In one aspect, the present invention provides an ophthalmic lens (e.g., an IOL) that includes an optic having an anterior surface and a posterior surface disposed about an optical axis. At least one of the surfaces (e.g., the anterior surface) has a profile characterized by superposition of a base profile and an auxiliary profile. The auxiliary profile can include an inner region, an outer region and a transition region between the inner and the outer regions, where an optical path difference across the transition region (i.e., the optical path difference between the inner and the outer radial boundaries of the transition region) corresponds to a non-integer fraction (e.g., ½) of a design wavelength (e.g., a wavelength of about 550 nm). | 01-21-2010 |
Myoung Chul Choi, Plano, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090163219 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER DATA CALL - A system, method, and computer readable medium for a data call setup comprises receiving an origination message by a radio call control (RCC) and by a main call control (MCC), receiving an assignment request message by the MCC and by the RCC, and receiving a traffic channel assignment message by a channel element control (CEC) and by the MCC. | 06-25-2009 |
| 20100087201 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER CALL ORIGINATION AND TERMINATION - A system, method, and computer readable medium for a mobile origination comprises receiving an origination request message by a main call control (MCC) from a radio call control (RCC), receiving an assignment request message by the RCC from the MCC, receiving a traffic channel assign message by a channel element control (CEC) and by the MCC from the RCC, receiving a call setup message by a selector distribution unit (SDU) from the MCC, and receiving a link active message by the CEC from the SDU. | 04-08-2010 |
| 20110028155 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER DATA CALL - A system, method, and computer readable medium for a data call setup comprises receiving an origination message by a radio call control (RCC) and by a main call control (MCC), receiving an assignment request message by the MCC and by the RCC, and receiving a traffic channel assignment message by a channel element control (CEC) and by the MCC. | 02-03-2011 |
| 20110281588 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER HANDOFF - A system, method, and computer readable medium for a softer handoff comprises receiving a Pilot Strength Measurement Message (PSMM) to request a handoff by a selector distribution unit (SDU), receiving a softer handoff request message by a channel element control (CEC), receiving a softer handoff request message by a radio call control (RCC), receiving a traffic channel assignment message by the CEC, and receiving an indication of an addition of a new sector for the softer handoff by the SDU. | 11-17-2011 |
| 20120015663 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER - A combined base station controller ( | 01-19-2012 |
Myoung-Taek Choi, Arlington, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100016965 | Accommodative IOL with Toric Optic and Extended Depth of Focus - In one aspect, the present invention provides an intraocular lens (IOL), which comprises at least two optics disposed in tandem along an optical axis, and an accommodative mechanism that is coupled to at least one of the optics and is adapted to adjust a combined optical power of the optics in response to natural accommodative forces of an eye in which the optics are implanted so as to provide accommodation. At least one of the optics has a surface characterized by a first refractive region, a second refractive region and transition region therebetween, where an optical phase shift of incident light having a design wavelength (e.g., 550 nm) across the transition region corresponds to a non-integer fraction of that wavelength. | 01-21-2010 |
| 20110238174 | ACCOMMODATING INTRAOCULAR LENS USING TRAPEZOIDAL PHASE SHIFT - An accommodating intraocular lens (AIOL) includes an optic adapted to produce a trapezoidal phase shift and a plurality of haptics. Each haptic extends from a haptic-optic junction to at least one transverse arm contacting a capsular bag of the eye, and each haptic has sufficient length and rigidity to stretch a capsular bag of the eye to contact ciliary muscles of the eye. The haptic-optic junctions vault the optic forward relative to the haptics and compression of the haptics by the ciliary muscles moves the anterior optic forward. A combined accommodative power produced by the motion of the anterior optic and the trapezoidal phase shift is at least 0.5 Diopters. | 09-29-2011 |
Noun Choi, Flower Mound, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110307617 | Method And Apparatus For Handling Peers With Dynamic IP Connectivity Status In Peer-To-Peer Networks - Method and apparatus for communication in a peer-to-peer (P2P) network are provided. The method comprises a first peer in the P2P network selecting a primary Internet Protocol (IP) address from a plurality of IP addresses associated with the first peer. The method further comprises the first peer providing the primary IP address to a second peer as an address the second peer is to use in initiating communication with the first peer. The apparatus comprises a user equipment (UE) that includes a processor configured such that the UE selects a primary IP address from plurality of IP addresses associated with the UE and registers the primary IP address in the P2P network. | 12-15-2011 |
| 20120076121 | Releasing Connections with Local GW When UE Moves Out of Residential/Enterprise Network Coverage - A method, system and device are provided for managing LIPA and/or SIPTO connection releases when UE moves out of residential/enterprise network coverage in case service continuity is not supported for the LIPA/SIPTO PDN connection(s). To address problems caused by not providing service continuity for LIPA/SIPTO PDN connections, the PDN connection/PDP context created in the HeNB/HNB by the MME/SGSN includes context information related to the UE indicating whether such connection is a LIPA PDN connection PDN connection or not. In addition, each UE may be configured to reconnect or not reconnect to the PDN corresponding to a certain APN or service, depending on how the PDN connection was disconnected by the network. | 03-29-2012 |
Noun Choi, Irving, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110170517 | SYSTEM AND METHOD FOR ENABLING SESSION CONTEXT CONTINUITY OF LOCAL SERVICE AVAILABILITY IN LOCAL CELLULAR COVERAGE - Local IP Access (LIPA) allows an IP-capable user equipment (UE) connected via a femto cell direct access to other IP-capable devices in the local IP network. Selected IP Traffic Offload (SIPTO) is used to offload selected types of IP traffic towards a defined IP network close to the UE's point of attachment to the access network. LIPA PDN Connectivity indicates a PDP Context or a PDN Connection that gives access to services located in the local IP network of the femto cell subsystem. SIPTO PDN Connectivity indicates a PDP Context or PDN Connection that allows offload of selected types of IP traffic towards a defined IP network close to the UE's point of attachment to the access network. Systems, devices and methods are described herein that enable the identification of the type of connectivity available to a UE and enable session continuity for local cellular coverage. | 07-14-2011 |
Suk Kyoon Choi, Katy, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110022368 | SYSTEM AND METHOD FOR WELL PERFORMANCE OPTIMIZATION - A system, software program, and method to evaluate the performance of a well in a subsurface reservoir are disclosed. A new well module is used to evaluate new wells to be placed in fluid communication with the subsurface reservoir. An existing well module is used to evaluate existing wells that are in fluid communication with the subsurface reservoir. Wells can be evaluated to calculate performance characteristics, optimize performance, resolve any associated performance issues, or a combination thereof. A well screening module is used to quickly calculate properties of a well. A visual display is used to display outputs from the new well module, the existing well module, or the well screening module. | 01-27-2011 |
Tae-Youl Choi, Frisco, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100285210 | MULTIFUNCTIONAL MICROPIPETTE BIOLOGICAL SENSOR - The fabrication and use of a multifunctional micropipette biological sensor for in-situ detection of temperature changes, ion conductivity, and light is described herein. | 11-11-2010 |
Wan Choi, Austin, TX US
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|---|---|---|
| 20110268103 | TRANSMISSION SIGNALING TECHNIQUES TO ENHANCE RECEIVER INTERFERENCE MITIGATION PERFORMANCE - Techniques are described that can be used to maximize the interference suppression capability of space-time coded systems by managing synchronous transmission signaling. To enhance the probability of the occurrence synchronous interference and accordingly increase interference cancellation capability at a receiver, a network of at least two transmitters in a network may utilize similar structured coding schemes and coordinate transmission so that the receiver receives co-channel signals synchronously. | 11-03-2011 |
Wonchang Choi, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100183925 | Cation-Substituted Spinel Oxide and Oxyfluoride Cathodes for Lithium Ion Batteries - The present invention includes compositions and methods of making cation-substituted and fluorine-substituted spinel cathode compositions by firing a LiMn | 07-22-2010 |
Yeong-Jun Choi, Cedar Park, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100096766 | Imprint Lithography System and Method - A loading unit, surface scanning module, and an imprint module may be integrated into a single tool. Template may be loaded on loading unit and positioned within imprint module. Substrate may then be loaded on loading unit and scanned defects using surface scanning module. If substrate passes inspection by surface scanning module, substrate may be positioned imprint module where formable material may be dispensed thereon and imprinted. The imprinted substrate may then be unloaded from imprinting module. | 04-22-2010 |
| 20100119637 | Method to Control an Atmosphere Between a Body and a Substrate - Systems to control an atmosphere about a substrate are described. The systems include a wall coupled to the substrate to create a resistance of the flow between different regions of the substrate. | 05-13-2010 |
| 20110140304 | IMPRINT LITHOGRAPHY TEMPLATE - Nano imprint lithography templates for purging of fluid during nano imprint lithography processes are described. The templates may include an inner channel and an outer channel. The inner channel constructed to provide fluid communication with a process gas supply to a region between the template and a substrate during the nano imprint lithography process. The outer channel constructed to evacuate fluid and/or confine fluid between the active area of template and the substrate. | 06-16-2011 |
Yoonsu Choi, Houston, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110213288 | Device And Method For Transfecting Cells For Therapeutic Uses - This invention generally relates to devices and methods for ex vivo or in vivo transfection of living cells using electroporation, in particular high throughput microfluidic electroporation, and to therapeutic uses of the transfected cells. | 09-01-2011 |
Younsung Choi, Plano, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20120078604 | METHOD FOR MINIMIZING TRANSISTOR AND ANALOG COMPONENT VARIATION IN CMOS PROCESSES THROUGH DESIGN RULE RESTRICTIONS - Various embodiments provide an integrated circuit (IC) design method and design kit for reducing context variations through design rule restrictions. The design method can be applied to components (e.g., analog blocks) with a context variation in an IC design. By drawing a cover layer over such components, context-variation-reduction design rule restrictions can be applied to reduce the context variations. | 03-29-2012 |
Youn Sung Choi, Plano, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20120074973 | ON-DIE PARAMETRIC TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS - An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters. | 03-29-2012 |
| 20120074980 | SCRIBE LINE TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS FOR ICs INCLUDING MOS DEVICES - An apparatus includes a plurality of die areas having integrated circuit (IC) die each having circuit elements for performing a circuit function, and scribe line areas between the die areas. At least one test module is formed in the scribe line areas. The test module includes a reference layout that includes at least one active reference MOS transistor that has a reference spacing value for each of a plurality of context dependent effect parameters, and a plurality of variant layouts. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing values for at least one of the plurality of context dependent effect parameters. | 03-29-2012 |