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Choi, NY

Changhwan Choi, Yorktown Heights, NY US

Patent application numberDescriptionPublished
20090108294SCALABLE HIGH-K DIELECTRIC GATE STACK - A stack comprising a dielectric interface layer, a high-k gate dielectric layer, a group IIA/IIIB element layer is formed in that order on a semiconductor substrate. A metal aluminum nitride layer and, optionally, a semiconductor layer are formed on the stack. The stack is annealed at a raised temperature, e.g., at about 1,000° C. so that the materials in the stack are mixed to form a mixed high-k gate dielectric layer. The mixed high-k gate dielectric layer is doped with a group IIA/IIIB element and aluminum, and has a lower effective oxide thickness (EOT) than a conventional gate stack containing no aluminum. The inventive mixed high-k gate dielectric layer is amenable to EOT scaling due to the absence of a dielectric interface layer, which is caused by scavenging, i.e. consumption of any dielectric interface layer, by the IIA/IIB elements and aluminum.04-30-2009
20100193896METHOD FOR NITRIDATION OF SHALLOW TRENCH ISOLATION STRUCTURE TO PREVENT OXYGEN ABSORPTION - A method for forming an isolation structure includes forming a trench in a semiconductor layer. At least a portion of the trench is filled with a dielectric material including oxygen. A region comprising nitrogen is formed in at least an upper portion of the dielectric material.08-05-2010
20100320547SCAVANGING METAL STACK FOR A HIGH-K GATE DIELECTRIC - A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y M12-23-2010
20110115027STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS - Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.05-19-2011
20110207280SCAVANGING METAL STACK FOR A HIGH-K GATE DIELECTRIC - A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y M08-25-2011

Patent applications by Changhwan Choi, Yorktown Heights, NY US

Injae Choi, Webster, NY US

Patent application numberDescriptionPublished
20090194936METHOD AND APPARATUS FOR RELIEVING STRESS IN A PRE-REGISTRATION NIP - A method of using a buckle for relieving the stresses in sheets caused by differential displacements of drive nips during the registration process includes creating a buckle between pre-registration nips and registration nips. The velocities of the pre-registration nips and registration nips are closely controlled so that the magnitude of buckle between them is large enough to relieve the stresses in the sheet during the registration process, yet small enough to not interfere with the registration process.08-06-2009
20100096795FRICTION RETARD FEEDER WITH IMPROVED SHEET SEPARATION - A substrate feeding apparatus and a printing machine is provided herein for feeding substrates from a substrate stack having a nudger roll being selectively movable between a first position and a second position. In the first position, the nudger roll is in contiguous contact with a first substrate of the substrate stack for advancing the first substrate from the substrate stack. The first substrate having a lead edge and a trail edge, with the lead edge leading in a direction of advancement. In the second position, the nudger roll is not in contiguous contact with the substrate stack or the first substrate. A feed roll for further advancing the first substrate in the direction of advancement. A retard member forming a nip with the feed roll. The retard member is used for separating the first substrate from an adjacent second substrate. A guide baffle extending between the substrate stack and the nip, with the guide baffle configured to contact, and to guide, the first substrate as it advances in the direction of advancement from the nudger roll to the nip. The guide baffle provides an angular change in direction to the first substrate as the first substrate advances from the substrate stack to the nip. The guide baffle is configured such that as the lead edge of the first substrate enters the nip, the first substrate has portions thereof spaced from the guide baffle, with the spaced portions sagging towards the guide baffle to provide the first substrate with a concave profile. The nudger roll moves from the first position to the second position after the lead edge of the first substrate enters the nip.04-22-2010
20110089627GATE SYSTEM DIVERTING SHEETS INTO MULTI-WAYS - According to aspects illustrated herein, there are provided systems for conveying a sheet article into an intended pathway. The multi-way gate system for diverting sheets into multiple pathways in a sheet conveying device includes at least three pathways for directing the sheet from the sheet conveying member in a particular direction. A single gate plate is between the sheet conveying member and the pathways. The single gate plate is rotatable about a single axis to direct the sheet exiting the sheet conveying member toward one of the pathways.04-21-2011
20110135371Printing system architecture with center cross-over and interposer by-pass path - A printing system comprises a paper path architecture for parallel printing using multiple marking engines. The media path configuration enables all the media feed trays to be located in one place, relative to the marking engines. A cross-over module is located between marking engines. The cross-over module can interleave media sheets that are being transported away from a first marking engine with the sheets being transported to the second marking engine. The cross-over module also includes a straight through path that enables media sheets to be transported directly to a finishing device without going through either marking engine. The marking engines include internal duplex loops such that media can be supplied to each engine in alternate groups. A merge module selectively merges the media which can then be further processed in a finishing transition module prior to communication to a finishing device.06-09-2011
20120032389GATE SYSTEM DIVERTING SHEETS INTO MULTI-WAYS - According to aspects illustrated herein, there are provided systems for conveying a sheet article into an intended pathway. The multi-way gate system for diverting sheets into multiple pathways in a sheet conveying device includes at least three pathways for directing the sheet from the sheet conveying member in a particular direction. A single gate plate is between the sheet conveying member and the pathways. The single gate plate is rotatable about a single axis to direct the sheet exiting the sheet conveying member toward one of the pathways.02-09-2012
20120098879SUBSTRATE MEDIA REGISTRATION SYSTEM AND METHOD IN A PRINTING SYSTEM - Embodiments described herein include a substrate media registration system in a printing system. The registration system can include a deskewing system, a reflexive system, and a controller. The deskewing system is configured to deskew substrate media. The reflexive system is configured to detect the lateral position of the substrate media and at least one of a lead edge and a trail edge of the substrate media being transported in the process direction. The controller is operatively coupled to the reflexive system and is configured to control ejection of ink from a print head system in response to detecting the lateral position of the substrate media and at least one of the lead edge and the trail edge of the substrate media.04-26-2012

Patent applications by Injae Choi, Webster, NY US

Jaeho Choi, Whitestone, NY US

Patent application numberDescriptionPublished
20100153313INTERFACE ADAPTATION SYSTEM - The invention relates to a system and method for automatically adapting a user interface for a computer operated device in response to the manner in which the device is physically operated and the conditions surrounding operation. The system provides sensors on or within a device in order to detect the physical position, identity, or orientation of an object used for interfacing with the device. The orientation of the device and the environmental conditions around the device are also determined. In turn, the system adapts the interactive control or input elements and/or the non-interactive elements of the UI in order to optimize usability of the device.06-17-2010

Patent applications by Jaeho Choi, Whitestone, NY US

Jihong Choi, Fishkill, NY US

Patent application numberDescriptionPublished
20110086445METHODS RELATING TO CAPACITIVE MONITORING OF LAYER CHARACTERISTICS DURING BACK END-OF-THE-LINE PROCESSING - Methods are provided that relate to the capacitive monitoring of characteristic pertaining to layer formed during the back end-of-the-line (BEOL) processing of a semiconductor device. In one embodiment, a method includes the steps of forming a first capacitor array including first and second overlying contacts each formed in a different one of the plurality of BEOL layers, measuring the interlayer capacitance between the first and second overlying contacts, and converting the measured interlayer capacitance to a distance between the first and second overlying contacts.04-14-2011
20110254139CMP-FIRST DAMASCENE PROCESS SCHEME - An improved metal interconnect is formed with reduced metal voids and dendrites. An embodiment includes forming a mask layer on a dielectric layer, forming openings in the mask and dielectric layers, depositing a planarization layer over the mask layer and filling the openings, planarizing to remove the mask layer, removing the planarization layer from the openings, and filling the openings with metal. The planarization step prior to depositing the metal removes the etch undercut that occurs during formation of the openings and reduces the aspect ratio in the openings, thereby improving metal fill uniformity.10-20-2011

Jong Hak Choi, Syosset, NY US

Patent application numberDescriptionPublished
20080223914Frangible Envelope Portion with Tear Line - Disclosed is to an easy-open envelope having a tear-line located within a length of the envelope's seam fastened to frangible portions of the envelope created by strategically placed perforations creating an envelope mailer with an integral opener that eliminates the need for using a knife or letter opener potentially damaging the envelope contents or using a finger which leaves the envelope ragged.09-18-2008
20080227059Educational Aid for Vocabulary and Recognition of Form Spatial Structure and Word Enigma Straws - Disclosed are educational straws having an end portion of a defined shape and the name of said shape displayed on the exterior body of the straw thereby instilling a cognitive recognition of a sequence of letters associated with the shape which will enhance vocabulary, spelling and object spatial recognition for a plurality of defined shapes09-18-2008
20080237246Beverage Container with Self Deploying Straw - Disclosed is a beverage container having an internal flexible straw having spaced apart flexure joints positioned to create pressure within the straw body so that when the pull tab is removed from its covering position of the beverage body port the stored energy within the straw flexure joint portions will extend the top portion of the straw through the body port opening into an operative position.10-02-2008

Juhyun Choi, Brooklyn, NY US

Patent application numberDescriptionPublished
20080200419Splicing Variant of TGF-beta2 and Uses Thereof - An alternatively spliced form of transforming growth factor-beta2 (TGF-β2), herein denoted Δ6-TGF-β2 is disclosed. Δ6-TGF-β2 differs from TGF-β2 in the sequence of the three C-terminal exons. This novel protein is secreted, induced by cytotoxic stress in hematopoietic stem cells, and specifically blocks the enhancing effects of TGF-β2 on adult stem cells. Δ6-TGF-β2 can be used to protect stem cells from cytotoxic stress, and to enhance maintenance of these cells in vitro during retroviral transduction. In addition, Δ6-TGF-β2 can be used to slow aging and extend longevity.08-21-2008

Kisik Choi, Hopwell Junction, NY US

Patent application numberDescriptionPublished
20110309455Gate-Last Fabrication of Quarter-Gap MGHK FET - A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.12-22-2011

Kisik Choi, Hopewell Junction, NY US

Patent application numberDescriptionPublished
20090039441MOSFET WITH METAL GATE ELECTRODE - Devices comprising, and method for fabricating, a MOSFET with a metal gate electrode are disclosed. In one embodiment, the MOSFET includes a first doped region configured to receive current from a current source, a second doped region configured to drain current from the first doped region when an electric field is modified between the first doped region and the second doped region, and a gate electrode configured to modify the electric field. The gate electrode may include a high-k layer, a hafnium-based metal layer formed above the high-k layer, and a polysilicon layer formed above the hafnium-based metal layer. In a further embodiment, the gate electrode further comprises a titanium-based metal layer formed between the hafnium-based metal layer and the polysilicon layer.02-12-2009
20090108294SCALABLE HIGH-K DIELECTRIC GATE STACK - A stack comprising a dielectric interface layer, a high-k gate dielectric layer, a group IIA/IIIB element layer is formed in that order on a semiconductor substrate. A metal aluminum nitride layer and, optionally, a semiconductor layer are formed on the stack. The stack is annealed at a raised temperature, e.g., at about 1,000° C. so that the materials in the stack are mixed to form a mixed high-k gate dielectric layer. The mixed high-k gate dielectric layer is doped with a group IIA/IIIB element and aluminum, and has a lower effective oxide thickness (EOT) than a conventional gate stack containing no aluminum. The inventive mixed high-k gate dielectric layer is amenable to EOT scaling due to the absence of a dielectric interface layer, which is caused by scavenging, i.e. consumption of any dielectric interface layer, by the IIA/IIB elements and aluminum.04-30-2009
20090294867DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL - Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.12-03-2009
20100193896METHOD FOR NITRIDATION OF SHALLOW TRENCH ISOLATION STRUCTURE TO PREVENT OXYGEN ABSORPTION - A method for forming an isolation structure includes forming a trench in a semiconductor layer. At least a portion of the trench is filled with a dielectric material including oxygen. A region comprising nitrogen is formed in at least an upper portion of the dielectric material.08-05-2010
20100213553METAL OXIDE SEMICONDUCTOR DEVICES HAVING BURIED GATE CHANNELS AND METHODS FOR FABRICATING THE SAME - Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a channel layer overlying the semiconductor substrate, forming a channel capping layer having a first surface overlying the channel layer, oxidizing the first surface of the channel capping layer, and depositing a high-k dielectric layer overlying the channel capping layer.08-26-2010
20100213555METAL OXIDE SEMICONDUCTOR DEVICES HAVING CAPPING LAYERS AND METHODS FOR FABRICATING THE SAME - Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a silicon oxide layer overlying the semiconductor substrate, forming a metal oxide gate capping layer overlying the silicon oxide layer, depositing a first metal gate electrode layer overlying the metal oxide gate capping layer, and removing a portion of the first metal gate electrode layer and the metal oxide gate capping layer to form a gate stack.08-26-2010
20100301401SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS THAT USE COMPRESSIVE MATERIAL WITH A REPLACEMENT GATE TECHNIQUE - A semiconductor device and related method of fabricating it are provided. An exemplary fabrication process begins by forming a gate structure overlying a layer of semiconductor material, the gate structure comprising a gate insulator overlying the layer of semiconductor material and comprising a temporary gate element overlying the gate insulator. The process continues by forming a layer of compressive material overlying the gate structure, and by removing a first portion of the compressive material to expose an upper surface of the temporary gate element, while leaving a second portion of the compressive material intact and external to sidewalls of the temporary gate element. Thereafter, at least a portion of the temporary gate element is removed, while leaving the second portion of the compressive material intact, resulting in a gate recess. The process continues by at least partially filling the gate recess with a gate electrode material.12-02-2010
20110198696FINNED SEMICONDUCTOR DEVICE WITH OXYGEN DIFFUSION BARRIER REGIONS, AND RELATED FABRICATION METHODS - A semiconductor device and related fabrication methods are provided. One exemplary fabrication method forms a fin arrangement overlying an oxide layer, where the fin arrangement includes one or more semiconductor fin structures. The method continues by nitriding exposed portions of the oxide layer without nitriding the one or more semiconductor fin structures, resulting in nitrided portions of the oxide layer. Thereafter, a gate structure is formed transversely overlying the fin arrangement, and overlying the exposed portions of the oxide layer. The nitrided portions of the oxide layer substantially inhibit diffusion of oxygen from the oxide layer into the gate structure.08-18-2011
20110309449INTERFACE-FREE METAL GATE STACK - A method of fabricating a gate stack for a transistor includes forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer.12-22-2011

Patent applications by Kisik Choi, Hopewell Junction, NY US

Kyung Ja Kay Choi, Great Neck, NY US

Patent application numberDescriptionPublished
20090289088Wig or hair piece box and form - An exemplary embodiment providing one or more improvements includes wig or hair piece boxes for both the efficient storage and display of wigs or hair pieces before sell, as well as providing simple, efficient and effective storage facilities for wigs or hair pieces for use of the consumer. The wig or hair piece boxes include a form which holds the wig or hair piece and preserves the curl, style, and one directional curl of the hair tip end on the wig or hair piece. This avoids the common problem of loss of original curl and style of the wig or hair piece which plagues conventional wig and hair piece boxes.11-26-2009
20110132942Jar shaped form for wig or hair piece storage - An exemplary embodiment providing one or more improvements includes an form which holds a hair extension and maintains the order and curl of the strands of hair. The form provides optimum display of the wig or hair extension evaluation by the prospective user. In addition, after purchase, the form provides a means for convenient space-saving storage of the hair extension which maintains the appearance of the hair extension.06-09-2011
20120006696Box and form for wig or hair piece - An exemplary embodiment providing one or more improvements includes wig or hair piece boxes which have a form comprised of a torus-shaped doughnut and a mandrel. In use, the wig or hair pieces are wrapped about the mandrel, the mandrel is placed within the lumen of the torus-shaped doughnut, and the curved portion of the wefts of hair are placed over the curved surface of the torus-shaped doughnut. The wefts of hair may be secured in place with a hairnet and the wig and form placed in a box for sale or storage by the consumer after sale. Embodiments allow the display before sale and convenient storage of wigs and hair pieces by the consumer while preserving the curl of the hair.01-12-2012
20120111742Wig or hair piece box and form - An exemplary embodiment providing one or more improvements includes wig or hair piece boxes for both the efficient storage and display of wigs or hair pieces before sell, as well as providing simple, efficient and effective storage facilities for wigs or hair pieces for use of the consumer. The wig or hair piece boxes include a form which holds the wig or hair piece and preserves the curl, style, and one directional curl of the hair tip end on the wig or hair piece. This avoids the common problem of loss of original curl and style of the wig or hair piece which plagues conventional wig and hair piece boxes.05-10-2012

Patent applications by Kyung Ja Kay Choi, Great Neck, NY US

Minkyung Grace Choi, Bayside, NY US

Patent application numberDescriptionPublished
20120035435ELECTROCARDIOGRAM MONITOR - A device is provided for sensing an electrocardiogram signal of a patient. The device includes a substrate and a plurality of electrodes mounted to the substrate. The plurality of electrodes are configured to sense an electrocardiogram signal of a patient when the plurality of electrodes are placed in contact with the patient. The device may include a strap configured to wrap around a portion of the patient wherein the substrate mounts to the strap. The device further may include a respiration sensor mounted to the strap.02-09-2012

Samuel S. Choi, Beacon, NY US

Patent application numberDescriptionPublished
20090017632METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES USING RIE PROCESS - A method for etching on a semiconductors at the back end of line using reactive ion etching. The method comprises reduced pressure atmosphere and a mixture of gases at a specific flow rate ratio during plasma generation and etching. Plasma generation is induced by a source radio frequency and anisotropic etch performance is induced by a second bias radio frequency.01-15-2009

Patent applications by Samuel S. Choi, Beacon, NY US

Samuel S. Choi, Hopewell Junction, NY US

Patent application numberDescriptionPublished
20110039413METHOD FOR FORMING TRENCHES HAVING DIFFERENT WIDTHS AND THE SAME DEPTH - A lithographic material stack including a photo-resist and an organic planarizing layer is combined with an etch process that generates etch residues over a wide region from sidewalls of etched regions. By selecting the etch chemistry that produces deposition of etch residues from the organic planarizing layer over a wide region, the etch residue generated at the sidewalls of the wide trench is deposited over the entire bottom surface of the wide trench. An etch residue portion remains at the bottom surface of the wide trench when the organic planarizing layer is etched through in the first trench region. The etch residue portion is employed in the next step of the etch process to retard the etch rate in the wide trench, thereby producing the same depth for all trenches in the material layer into which the pattern of the lithographic material stack is transferred.02-17-2011

Sheung S. Choi, Roslyn, NY US

Patent application numberDescriptionPublished
20110219820Brilliance enhancing jewelry prong setting - A ring with a composite Diamond Head setting is described that includes a head portion and a base portion. The head portion includes at least one channel structure that defines a marquise-cut diamond shaped indentation adapted to be positioned with a plurality of multiple shaped diamonds in a juxtaposition arrangement to form a clustered Diamond Head that creates an illusion of a big marquise-cut shaped diamond over the head portion. The head portion can include a circular or pear shaped indentation adapted to be positioned with multiple shaped diamonds in a juxtaposition arrangement to form a clustered Diamond Head that creates an illusion of a big a circular or pear shape shaped diamond over the head portion.09-15-2011

Sungyeun Choi, Tarrytown, NY US

Patent application numberDescriptionPublished
20100147188Graphite nanoplatelets and compositions - Disclosed are graphite nanoplatelets produced by a process which comprises thermal plasma expansion of intercalated graphite to produce expanded graphite followed by exfoliation of the expanded graphite, where the exfoliation step is selected from ultrasonication, wet milling and controlled caviation and where greater than 95% of the graphite nanoplatelets have a thickness of from about 0.34 nm to about 50 nm and a length and width of from about 500 nm to about 50 microns. The intercalated graphite is intercalated for example with a mixture of sulfuric and nitric acids. The plasma reactor for example employs an RF induction plasma torch. All three exfoliation methods are performed in an organic solvent or water. The exfoliation steps may be performed with the aid of for example a nonionic surfactant. Also disclosed are plastic, ink, coating, lubricant or grease compositions comprising the graphite nanoplatelets.06-17-2010

Tayoung Choi, Rochester, NY US

Patent application numberDescriptionPublished
20110014535METHOD TO IMPROVE RELIABILITY OF A FUEL CELL SYSTEM USING LOW PERFORMANCE CELL DETECTION AT LOW POWER OPERATION - A system and method for detecting a low performing cell in a fuel cell stack using measured cell voltages. The method includes determining that the fuel cell stack is running, the stack coolant temperature is above a certain temperature and the stack current density is within a relatively low power range. The method further includes calculating the average cell voltage, and determining whether the difference between the average cell voltage and the minimum cell voltage is greater than a predetermined threshold. If the difference between the average cell voltage and the minimum cell voltage is greater than the predetermined threshold and the minimum cell voltage is less than another predetermined threshold, then the method increments a low performing cell timer. A ratio of the low performing cell timer and a system run timer is calculated to identify a low performing cell.01-20-2011
20110086286METHOD TO PERFORM ADAPTIVE VOLTAGE SUPPRESSION OF A FUEL CELL STACK BASED ON STACK PARAMETERS - A system and method for maintaining the voltage of fuel cells in the fuel cell stack below a predetermined maximum voltage. The method determines a desired voltage set-point value that defines a predetermined maximum fuel cell voltage value and uses the voltage set-point value and an average fuel cell voltage to generate an error value there-between. The method generates a minimum gross power prediction value using the modified voltage set-point value to prevent the fuel cell voltages from going above the predetermined maximum fuel cell voltage value and generating a supplemental power value based on the minimum gross power prediction value and the error value to determine how much power needs to be drawn from the stack to maintain the fuel cell voltage below the predetermined maximum voltage value. The method uses the supplemental power value to charge the battery or operate an auxiliary load coupled to the stack.04-14-2011
20110200895METHOD TO AUTOMATICALLY ENABLE/DISABLE STACK RECONDITIONING PROCEDURE BASED ON FUEL CELL STACK PARAMETER ESTIMATION - A system and method for determining when to trigger reconditioning of a fuel cell stack and when to disable the reconditioning of the fuel cell stack. In one embodiment, the stack reconditioning is triggered when a maximum stack power estimation falls below a first predetermined power threshold. The reconditioning of the stack can be disabled so it is not performed when the trigger occurs if the reconditioning process does not raise the maximum power estimation above a second predetermined power threshold or the time from one reconditioning trigger to a next reconditioning trigger is less than a predetermined time threshold, or both.08-18-2011
20110213516HEEL AND TOE DRIVING ON FUEL CELL VEHICLE - A system and method for providing nearly instantaneous power in a fuel cell vehicle. The method includes monitoring the brake pedal angle and the accelerator pedal angle of the vehicle, and if the vehicle driver is pressing both the brake pedal and the accelerator pedal at the same time and the vehicle is in a drive gear, activating a heel and toe mode. When the heel and toe mode is activated, the speed of a cathode compressor is increased to a predetermined speed set-point, which is higher than the normal compressor speed for the pedal position. Thus, when the vehicle brake is removed, the compressor speed is high enough to provide enough air to the cathode, so that the stack can generate nearly immediate power.09-01-2011

Yejin Choi, Ithaca, NY US

Patent application numberDescriptionPublished
20110264640Using External Sources for Sponsored Search AD Selection - A system and a system are provided for using external sources (e.g., landing pages) for sponsored search ad selection. In one example, the system identifies one or more regions of an external source. The one or more regions are relevant to a query. The external source includes a source that includes relevant data that is usable for augmenting an ad selection process. The system extracts one or more features from the one or more regions. The system determines which of the one or more features are relevant for item indexing. The system then augments an item selection process by using the one or more features that are relevant for item indexing.10-27-2011

Yongwon Choi, New York, NY US

Patent application numberDescriptionPublished
20120135496Protein Belonging to the TNF Superfamily Involved in Signal Transduction, Nucleic Acids Encoding Same and Methods of Use Thereof - A method of modulating immune response in an animal is disclosed. Such a method interacting the immature dendritic cells from the animal with an antigen ex vivo so that the immature dendritic cells present the antigen on their surfaces, inducing maturation of the immature dendritic cells ex vivo, and contacting the mature dendritic cells ex vivo with a modulator comprising TRANCE, conservative variants thereof, fragments thereof, analogs or derivatives thereof, or a fusion protein comprising the amino acid sequence of TRANCE, conservative variants thereof, or fragments thereof. After contacting the modulator ex vivo, the mature dendritic cells are introduced into the animal. As a result, immune response in the animal towards the antigen is modulated relative to the immune response against the antigen in an animal in which dendritic cells did not interact with the antigen ex vivo, and did not contact a modulator ex vivo. Preferably, the method of the present invention results in increasing immune response towards the antigen in the animal.05-31-2012

Youngjin Choi, Hopewell Junction, NY US

Patent application numberDescriptionPublished
20100178771Methods of Forming Dual-Damascene Metal Interconnect Structures Using Multi-Layer Hard Masks - Methods of forming dual-damascene metal interconnect structures include forming an electrically insulating layer on an integrated circuit substrate and then forming a hard mask layer on the electrically insulating layer. The hard mask layer may include a stacked composite of at least four electrically insulating material layers therein. The hard mask layer may also have separate trench and via patterns therein that are respectively defined by at least first and second ones of the electrically insulating material layers and at least third and fourth ones of the electrically insulating material layers.07-15-2010

Yu Choi, Brooklyn, NY US

Patent application numberDescriptionPublished
20090287498SYSTEM AND METHOD FOR STREAMLINED REGISTRATION OF ELECTRONIC PRODUCTS OVER A COMMUNICATION NETWORK AND FOR VERIFICATION AND MANAGEMENT OF INFORMATION RELATED THERETO - The system and method of the present invention provide integrated or embedded components, for electronic (or other) products, each operable to securely store and selectively provide access to, a unique ID (UID) previously assigned to its corresponding specific product, where the UID of each product is registered with one or more particular UID registration centers over at least one communication network, and associated with one or more data records stored in a corresponding database file at the particular UID registration center, the data records being inclusive of information related to the product, the product purchase history, current ownership, etch, and wherein one or more authorized parties may subsequently advantageously utilize at least one UID (and optionally a verifier) to access, verify, edit, transfer, transmit, and/or otherwise manage at least one information item related to the one or more corresponding registered products in their UID registration center database file. Also provided is an optimized process for verifiable transfer of ownership rights between a product's authorized owner and intended recipient, the transfer process being implemented over at least one communication network with graphical user interfaces provided for each party, where the transfer of ownership rights involves association of the product's UID with the receiving party's data record and confirming ownership transfer, and optional transfer of additional product-related information from the former product owner to the current recipient. 11-19-2009

Yungran Choi, Webster, NY US

Patent application numberDescriptionPublished
20080266580Scaling methods for binary image data - The embodiments describe calculating and store scaling information based on processing input binary image data. By manipulating data that is received in binary format, the most cost effective method for scaling may be chosen. The input image data is scanned, a resolution (e.g., for display or output) is determined and a scaling method is determined. If the input binary image data needs to be scaled down to a smaller resolution, the binary image data is processed and scaled and then converted to grayscale image data. If the image data must be scaled to a larger resolution, the input binary image data is first converted to grayscale image data before processing using a segmentation tag-based scaling method. The scaled image data may then be output to an output device, such as a display, printer, or image output terminal.10-30-2008

Yu Yung Choi, Brooklyn, NY US

Patent application numberDescriptionPublished
20090144074SYSTEM AND METHOD FOR STREAMLINED REGISTRATION OF ELECTRONIC PRODUCTS OVER A COMMUNICATION NETWORK AND FOR VERIFICATION AND MANAGEMENT OF INFORMATION RELATED THERETO - The system and method of the present invention provide integrated or embedded components, for electronic (or other) products, each operable to securely store and selectively provide access to, a unique ID (UID) previously assigned to its corresponding specific product, where the UID of each product is registered with one or more particular UID registration centers over at least one communication network, and associated with one or more data records stored in a corresponding database file at the particular UID registration center, the data records being inclusive of information related to the product, the product purchase history, current ownership, etc., and wherein one or more authorized parties may subsequently advantageously utilize at least one UID (and optionally a verifier) to access, verify, edit, transfer, transmit, and/or otherwise manage at least one information item related to the one or more corresponding registered products in their UID registration center database file. Also provided is an optimized process for verifiable transfer of ownership rights between a product's authorized owner and intended recipient, the transfer process being implemented over at least one communication network with graphical user interfaces provided for each party, where the transfer of ownership rights involves association of the product's UID with the receiving party's data record and confirming ownership transfer, and optional transfer of additional product-related information from the former product owner to the current recipient.06-04-2009
20090289774SECURE ELECTROMAGNETIC DATA STORAGE ELEMENT HAVING A PLURALITY OF SELECTIVELY DETERMINED SWITCHABLE SECURITY MODES - The apparatus of the present invention are directed to an selectively accessible electromagnetically resonant data storage element (implemented as a resonant tag, card, and/or embedded element), that is selectively responsive to predetermined electromagnetic interrogation thereof, that comprises a novel membrane switch component for enabling a user to selectively enable and/or disable interrogatory access to the resonant component, to protect from unauthorized interrogation thereof (hereinafter “MSRDS element”). The inventive MSRDS element comprises a top circuitry layer, a bottom circuitry layer, which includes a microchip, a plurality of contact pads and an antenna, an insulation spacer layer, a pressure layer retention component, and an optional EM/EMI shielding layer. The membrane switch may be formed through a combination of aligned and configured subcomponents of at least a portion of the element's layers. In one embodiment thereof, the pressure layer retention component may be advantageously utilized to maintain the membrane switch in a pressed down position to thereby enable the MSRDS element to function continuously (i.e., in an Always-ON security mode), until such time that the pressure layer retention component is removed. In this exemplary embodiment of the MSRDS element, for example used in conjunction with consumer products, when a consumer purchases a product that has been provided with the MSRDS element, they remove (e.g., peel off, etc.) the pressure layer retention component to change the element to an Always-OFF security mode, such that the MSRDS element is only accessible to electromagnetic interrogation thereof when the membrane switch is held down. Therefore, the MSRDS element of the present invention provides a greater level of data security advantageously balanced with convenience—it is freely accessible prior to acquisition thereof by a user, and is thereafter easily made secure by the user, who is provided with the capability of readily and selectively enabling access to the data stored therein.11-26-2009
20090303050SECURE ELECTROMAGNETIC DATA STORAGE ELEMENT HAVING A PLURALITY OF SELECTIVELY DETERMINED SWITCHEABLE SECURITY MODES - The apparatus of the present invention are directed to an selectively accessible electromagnetically resonant data storage element (implemented as a resonant tag, card, and/or embedded element), that is selectively responsive to predetermined electromagnetic interrogation thereof, that comprises a novel membrane switch component for enabling a user to selectively enable and/or disable interrogatory access to the resonant component, to protect from unauthorized interrogation thereof (hereinafter “MSRDS element”). The inventive MSRDS element comprises a top layer, a bottom circuitry layer, which includes a microchip, a plurality of contact pads and an antenna, an insulation spacer layer, a pressure layer retention component, and an optional EMI shielding layer. The membrane switch may be formed through a combination of aligned and configured subcomponents of at least a portion of the element's layers. In one embodiment thereof, the pressure layer retention component may be advantageously utilized to maintain the membrane switch in a pressed down position to thereby enable the MSRDS element to function continuously (i.e., in an Always-ON mode), until such time that the pressure layer retention component is removed. In this exemplary embodiment of the MSRDS device, for example used in conjunction with consumer products, when a consumer purchases a product that has been provided with the MSRDS element, they remove (e.g., peel off, etc.) the pressure layer retention component to change the element to an Always-OFF mode, such that the MSRDS element is only accessible to electromagnetic interrogation thereof, when the membrane switch is held down. Therefore, the MSRDS device of the present invention provides a greater level of data security advantageously balanced with convenience—it is freely accessible prior to acquisition thereof by a user, and is thereafter easily made secure by the user, who is provided with the capability of readily and selectively enabling access to the data stored therein.12-10-2009
20110147467ENHANCED PERFORMANCE AND SECURITY RFID DEVICE - The present invention is directed to a selectively accessible enhanced radio-frequency identification (RFID) device, that is enhanced performance and security by selectively responsive to predetermined electromagnetic interrogation thereof, that comprises an enhanced component for enabling a user to adjust readable distances and selectively enable or disable interrogatory access to the enhanced RFID device, to protect from unauthorized interrogation thereof. The inventive enhanced RFID device comprises an antenna, a microchip and at least one enhanced component. The enhanced component may use “Electromagnetic Induction” to the antenna to increase performance and “Electromagnetic Shield”, to cover the antenna. In one embodiment thereof, the enhanced RFID device may be advantageously utilizing retention component to keep closed it in an Always-OFF mode, such that the enhanced RFID device is only accessible to electromagnetic interrogation thereof, when the enhanced RFID device is open to an Always-ON mode. Therefore, the enhanced RFID device of the present invention provides an inventively user controllable, two functions in one of enhanced component, for enhanced performance and greater level of data security advantageously balanced with convenience—it is freely accessible prior to acquisition thereof by a user, and is thereafter easily made secure by the user, who is provided with the capability of readily and selectively enabling access to the data stored therein.06-23-2011