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Choi, Icheon-Si
Geun Min Choi, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110212610 | METHODS OF FORMING DUAL GATE OF SEMICONDUCTOR DEVICE - Disclosed herein is a method for forming a dual gate of a semiconductor device. The method comprises the steps of forming a first polysilicon layer doped with p-type impurity ions and a second polysilicon layer doped with n-type impurity ions on a first region and a second region of a semiconductor substrate, respectively, and sequentially subjecting the surfaces of the first and second polysilicon layers to wet cleaning, drying, and dry cleaning. The wet cleaning is performed by using a sulfuric acid peroxide mixture (SPM), a buffered oxide etchant (BOE), and Standard Clean-1 (SC-1) as cleaning solutions. | 09-01-2011 |
| 20110212611 | METHODS OF FORMING DUAL GATE OF SEMICONDUCTOR DEVICE - Disclosed herein is a method for forming a dual gate of a semiconductor device. The method comprises the steps of forming a first polysilicon layer doped with p-type impurity ions and a second polysilicon layer doped with n-type impurity ions on a first region and a second region of a semiconductor substrate, respectively, and sequentially subjecting the surfaces of the first and second polysilicon layers to wet cleaning, drying, and dry cleaning. The wet cleaning is performed by using a sulfuric acid peroxide mixture (SPM), a buffered oxide etchant (BOE), and Standard Clean-1 (SC-1) as cleaning solutions. | 09-01-2011 |
Hae Rang Choi, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110241726 | ON-DIE TERMINATION CIRCUIT - An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals. | 10-06-2011 |
| 20110267124 | CLOCK SIGNAL DUTY CORRECTION CIRCUIT - A clock signal duty correction circuit includes: a first transition timing control unit configured to generate a first control signal for controlling a rising timing of a duty correction clock signal by using a clock signal; a second transition timing control unit configured to generate a second control signal for varying a falling timing of the duty correction clock signal by using the clock signal according to a code signal; and a differential buffer unit configured to generate the duty correction clock signal, whose rising time or falling time is adjusted, in response to the first control signal and the second control signal. | 11-03-2011 |
Hong Sok Choi, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120005397 | SENSE AMPLIFIER AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - A sense amplifier is configured to transfer data on a first data I/O line to a second data I/O line or to transfer data on the second data I/O line to the first data I/O line. The first data I/O line is substantially continuously coupled to the second data I/O line during an active operation. | 01-05-2012 |
Ik Soo Choi, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090269924 | Method for Forming Fine Pattern by Spacer Patterning Technology - In a method for forming a fine pattern, a target layer to be patterned is formed on a semiconductor substrate and a polysilicon layer is formed on the target layer. A partition is then formed on the polysilicon layer with an amorphous carbon layer pattern. A spacer is attached to a sidewall of the partition. Thereafter, the spacer is divided into bar patterns by selectively removing the partition. A polysilicon layer pattern is formed by selectively etching a portion of the poly silicon layer exposed by the divided bar patterns and then a target layer pattern is formed by selectively etching a portion of the target layer exposed by the polysilicon layer pattern. | 10-29-2009 |
Jae Seung Choi, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080295059 | Method for Correcting Optical Proximity Effect - A method of correcting an optical proximity effect may include the steps of: fabricating a test mask having test patterns; projecting patterns on a wafer using the test mask; measuring line widths of the patterns formed on the wafer; and executing a model calibration using the measured line widths and writing a correction recipe. The entire area of the wafer chip may be divided into a plurality of templates. An optical proximity correction may be executed on one of the templates and it may be verified that the optical proximity correction was executed properly on another template. The data for the templates that pass a verification may be merged and final data may be written using the merged data. A photomask may be fabricated using the final data. | 11-27-2008 |
| 20090170318 | METHOD FOR FORMING PATTERN OF SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises performing a CMP process using an oxide film as an etching barrier film to maintain a polysilicon layer having a large open area. A word line pattern, a DSL pattern, and a SSL pattern that are formed by a first patterning process are not additionally blocked, and the oxide film is used as an etching barrier to obtain an accurate overlay between patterns and improve CD uniformity, thereby improving a characteristic of the device. | 07-02-2009 |
| 20100209825 | EXPOSURE MASK AND METHOD FOR FORMING SEMICONDUCTOR DEVICE BY USING THE SAME - The present invention is the thing about exposure mask and manufacturing method of semiconductor device using the same | 08-19-2010 |
| 20120100469 | EXPOSURE MASK AND METHOD FOR FORMING SEMICONDUCTOR DEVICE BY USING THE SAME - The present invention is the thing about exposure mask and manufacturing method of semiconductor device using the same | 04-26-2012 |
Joong Il Choi, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080261373 | Method of fabricating semconductor device - A method of fabricating a semiconductor device includes forming a buffer insulating film over a semiconductor substrate including a conductive pattern. The buffer insulating film is etched using a storage node mask to form a buffer insulating pattern exposing the conductive pattern. The buffer insulating pattern defines a region wider than a storage node region. An etch stop film is formed over the conductive pattern and the buffer insulating pattern. An interlayer insulating film is formed over the etch stop film. The interlayer insulating film is etched using the storage node mask to expose the etch stop film. The exposed etch stop film is etched to form the storage node region exposing conductive pattern. A lower storage node is formed over the storage node region. | 10-23-2008 |
| 20100258906 | CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming a buffer insulating film over a semiconductor substrate including a conductive pattern. The buffer insulating film is etched using a storage node mask to form a buffer insulating pattern exposing the conductive pattern. The buffer insulating pattern defines a region wider than a storage node region. An etch stop film is formed over the conductive pattern and the buffer insulating pattern. An interlayer insulating film is formed over the etch stop film. The interlayer insulating film is etched using the storage node mask to expose the etch stop film. The exposed etch stop film is etched to form the storage node region exposing conductive pattern. A lower storage node is formed over the storage node region. | 10-14-2010 |
Kang Sik Choi, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100276739 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The semiconductor device includes a device isolation structure formed in a semiconductor substrate to define an active region, a bridge type channel structure formed in the active region, and a coaxial type gate electrode surrounding the bridge type channel structure of a gate region. The bridge type channel structure is separated from the semiconductor substrate thereunder by a predetermined distance in a vertical direction. | 11-04-2010 |
| 20110057261 | SEMICONDUCTOR DEVICE HAVING RECESS CHANNEL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a recess channel structure includes a semiconductor substrate having a recess formed in a gate forming area in an active area; an insulation layer formed in the semiconductor substrate so as to define the active area and formed so as to apply a tensile stress in a channel width direction; a stressor formed in a surface of the insulation layer and formed so as to apply a compressive stress in a channel height direction; a gate formed over the recess in the active area; and source/drain areas formed in a surface of the active area at both side of the gate. | 03-10-2011 |
Seong Sik Choi, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120082324 | VIBRATION EARPHONE - The present invention relates to a vibration earphone that improves the efficiency of sound output from the earphone by outputting vibrations for the high sound frequency range through a mastoid and by simultaneously outputting vibrations for the low frequency range through a cylindrical low sound transmitting member. The vibration earphone comprises a vibration member for outputting sound through vibrations and including a face plate, a voice coil, a basket with a magnet coupled thereto, and a cover; the low sound transmitting member housing the vibration member therein, for outputting vibrations for low sound through an external wall inside an ear; and a mastoid for outputting vibrations for the high sound frequency range generated from the face plate through a projection passing through the low sound transmitting member and inserted in and coupled to a hole defined in a central portion of the face plate of the vibration member. | 04-05-2012 |
Shin-Gyu Choi, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100055866 | METHOD OF FORMING TRANSISTOR IN SEMICONDUCTOR DEVICE - A method of forming a transistor in a semiconductor device includes forming device isolation structures in a substrate to define an active region. An oxide-based layer and a nitride-based layer are then formed between the active region and the device isolation structures. A predetermined gate region is etched in the active region to form a recess region. The damage layers are formed by a tilted ion implantation process using neutral elements on portions of the oxide-based layer exposed at the sidewalls of the recess region and other portions of the oxide-based layer below the recess region. The damage layers are then removed, thus causing a portion of the active region exposed at the bottom of the recess region to protrude. | 03-04-2010 |
Soo Young Choi, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110037931 | Fringe-Field-Switching-Mode Liquid Crystal Display and Method of Manufacturing the Same - Provided are a fringe-field-switching (FFS)-mode liquid crystal display (LCD) and a method of manufacturing the same. The FFS-mode LCD includes a transparent common electrode, a conductive reflection structure electrically connected to the transparent common electrode, and a transparent pixel electrode formed on the conductive reflection structure and including a plurality of slits. The transparent common electrode is formed on a region including a data line and a gate line so that respective unit pixel regions can be electrically connected to one another. | 02-17-2011 |
| 20110109861 | Fringe Field Switching Mode Liquid Crystal Display Device and Method of Fabricating the Same - Provided is a liquid crystal display including a transparent pixel electrode and a transparent common electrode in a pixel region to drive liquid crystals. The transparent common electrode includes a plurality of slits and is configured to open at least a portion of a switching device to connect unit pixels, the slits have an angle of 5 to 10° with respect to a gate line, and a rubbing direction of a liquid crystal layer is substantially parallel to a gate direction. Therefore, it is possible to provide the liquid crystal display capable of removing factors decreasing an aperture ratio, preventing light from leaking, and further improving internal reflection. | 05-12-2011 |
Suk Choi, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110244751 | FRINGE FIELD SWITCHING MODE LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF - Provided is a fringe field switching mode liquid crystal display. The fringe field switching mode liquid crystal display includes a transparent common electrode having a predetermined shape and formed within the pixel area to adjust light transmittance by applying a voltage to the liquid crystal layer, and a transparent pixel electrode having a plurality of slits and formed above the transparent common electrode with an insulating layer interposed between the transparent common electrode and the transparent pixel electrode. A rubbing direction for aligning the liquid crystal layer is within 5° with respect to a direction of the gate line to remove a light shielding region above the data line, one end of the transparent common electrode is arranged between the data line and the transparent pixel electrode, and a distance between the transparent common electrode and the transparent pixel electrode is regulated with respect to the data line. | 10-06-2011 |
Won Beom Choi, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120119815 | SWITCHING CIRCUIT OF SEMICONDUCTOR APPARATUS - A switching circuit of a semiconductor apparatus includes a first switching unit configured to substantially prevent a leakage current applied from an outside and simultaneously switch a first signal with a first high voltage bias level, and a second switching unit configured to switch a second signal with a second high voltage bias according to the first high voltage bias level. The first switching unit and the second switching unit are selectively switched by a first enable signal and a second enable signal, which are applied from an outside, to generate a global bias signal. | 05-17-2012 |
Yong-Soo Choi, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090124082 | SLURRY FOR POLISHING RUTHENIUM AND METHOD FOR POLISHING USING THE SAME - A slurry for polishing a ruthenium layer comprises distilled water, sodium periodate (NaIO | 05-14-2009 |
Young Geun Choi, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110023741 | FUSE INFORMATION DETECTION CIRCUIT - A fuse information detection circuit includes a fuse unit comprising a plurality of fuse sets and configured to output a plurality of fuse state signals, in parallel, at different levels according to whether fuses of the plurality of fuse sets are cut, a signal alignment unit configured to receive and store the plurality of fuse state signals and sequentially output the plurality of fuse state signals whenever a read pulse is inputted, and a fuse information signal generation unit configured to generate a fuse information signal by counting output of the signal alignment unit whenever the read pulse is inputted. | 02-03-2011 |